提交 · 234b48e9c68759aea78ff5a1e49c2ba806cd1d83 · openeuler / qemu

15 6月, 2018 3 次提交

target/arm: Implement SVE Permute - Interleaving Group · 234b48e9

由 Richard Henderson 提交于 6月 15, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-5-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

234b48e9

target/arm: Implement SVE Permute - Predicates Group · d731d8cb

由 Richard Henderson 提交于 6月 15, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-4-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

d731d8cb

target/arm: Implement SVE Permute - Unpredicated Group · 30562ab7

由 Richard Henderson 提交于 6月 15, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-3-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

30562ab7

19 5月, 2018 23 次提交

target/arm: Implement SVE Permute - Extract Group · b94f8f60

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-26-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

b94f8f60

target/arm: Implement SVE Integer Wide Immediate - Predicated Group · f25a2361

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-25-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

f25a2361

target/arm: Implement SVE Bitwise Immediate Group · e1fa1164

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-24-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

e1fa1164

target/arm: Implement SVE Element Count Group · 24e82e68

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-23-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

24e82e68

target/arm: Implement SVE floating-point trig select coefficient · a1f233f2

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-22-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

a1f233f2

target/arm: Implement SVE floating-point exponential accelerator · 0762cd42

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-21-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

0762cd42

target/arm: Implement SVE Compute Vector Address Group · 4b242d9c

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-20-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

4b242d9c

target/arm: Implement SVE Bitwise Shift - Unpredicated Group · d9d78dcc

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-19-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

d9d78dcc

target/arm: Implement SVE Stack Allocation Group · 96f922cc

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-18-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

96f922cc

target/arm: Implement SVE Index Generation Group · 9a56c9c3

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-17-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

9a56c9c3

target/arm: Implement SVE Integer Arithmetic - Unpredicated Group · fea98f9c

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-16-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

fea98f9c

target/arm: Implement SVE Integer Multiply-Add Group · 96a36e4a

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-15-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

96a36e4a

target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group · afac6d04

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-14-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

afac6d04

target/arm: Implement SVE bitwise shift by wide elements (predicated) · fe7f8dfb

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-13-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

fe7f8dfb

target/arm: Implement SVE bitwise shift by vector (predicated) · 27721dbb

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-12-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

27721dbb

target/arm: Implement SVE bitwise shift by immediate (predicated) · ccd841c3

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-11-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

ccd841c3

target/arm: Implement SVE Integer Reduction Group · 047cec97

由 Richard Henderson 提交于 5月 18, 2018

Excepting MOVPRFX, which isn't a reduction.  Presumably it is
placed within the group because of its encoding.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-10-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

047cec97

target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group · f97cfd59

由 Richard Henderson 提交于 5月 18, 2018

Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-9-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

f97cfd59

target/arm: Implement SVE Predicate Misc Group · 028e2a7b

由 Richard Henderson 提交于 5月 18, 2018

Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-8-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

028e2a7b

target/arm: Implement SVE Predicate Logical Operations Group · 516e246a

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-7-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

516e246a

target/arm: Implement SVE predicate test · 9e18d7a6

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-6-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

9e18d7a6

target/arm: Implement SVE load vector/predicate · d1822297

由 Richard Henderson 提交于 5月 18, 2018

Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-5-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

d1822297

target/arm: Add SVE decode skeleton · 38388f7e

由 Richard Henderson 提交于 5月 18, 2018

Including only 4, as-yet unimplemented, instruction patterns
so that the whole thing compiles.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-3-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

38388f7e