1. 17 7月, 2011 3 次提交
  2. 13 7月, 2011 2 次提交
    • P
      exec.c: Fix calculation of code_gen_buffer_max_size · a884da8a
      Peter Maydell 提交于
      When calculating the point at which we should not try to put another
      TB into the code gen buffer, we have to allow not just for OPC_MAX_SIZE
      but OPC_BUF_SIZE. This is because the target translate.c will only
      stop when an instruction has put it past the OPC_MAX_SIZE limit, so
      we have to include the MAX_OP_PER_INSTR margin which that final insn
      might have used.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      a884da8a
    • A
      exec: add endian specific phys ld/st functions · 1e78bcc1
      Alexander Graf 提交于
      Device code some times needs to access physical memory and does that
      through the ld./st._phys functions. However, these are the exact same
      functions that the CPU uses to access memory, which means they will
      be endianness swapped depending on the target CPU.
      
      However, devices don't know about the CPU's endianness, but instead
      access memory directly using their own interface to the memory bus,
      so they need some way to read data with their native endianness.
      
      This patch adds _le and _be functions to ld./st._phys.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      1e78bcc1
  3. 27 6月, 2011 1 次提交
  4. 24 6月, 2011 1 次提交
  5. 19 6月, 2011 4 次提交
  6. 12 6月, 2011 1 次提交
  7. 08 6月, 2011 1 次提交
  8. 04 6月, 2011 1 次提交
  9. 01 6月, 2011 1 次提交
  10. 23 5月, 2011 1 次提交
  11. 20 5月, 2011 2 次提交
  12. 08 5月, 2011 2 次提交
  13. 05 5月, 2011 2 次提交
  14. 02 5月, 2011 2 次提交
  15. 20 4月, 2011 1 次提交
  16. 13 4月, 2011 2 次提交
  17. 07 4月, 2011 2 次提交
  18. 17 3月, 2011 1 次提交
  19. 16 3月, 2011 1 次提交
  20. 15 3月, 2011 1 次提交
  21. 13 3月, 2011 1 次提交
  22. 11 3月, 2011 1 次提交
    • V
      Fix performance regression in qemu_get_ram_ptr · 7d82af38
      Vincent Palatin 提交于
      When the commit f471a17e converted the
      ram_blocks structure to QLIST, it also removed the conditional check before
      switching the current block at the beginning of the list.
      
      In the common use case where ram_blocks has a few blocks with only one
      frequently accessed (the main RAM), this has a performance impact as it
      performs the useless list operations on each call (which are on a really
      hot path).
      
      On my machine emulation (ARM on amd64), this patch reduces the
      percentage of CPU time spent in qemu_get_ram_ptr from 6.3% to 2.1% in the
      profiling of a full boot.
      Signed-off-by: NVincent Palatin <vpalatin@chromium.org>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      7d82af38
  23. 14 2月, 2011 1 次提交
  24. 11 2月, 2011 1 次提交
  25. 16 1月, 2011 1 次提交
    • B
      tcg/sparc64: fix segfault · 4cd31ad2
      Blue Swirl 提交于
      With current OpenBSD, code_gen_buffer was mapped 8GB away from
      text segment. Then any helpers were beyond the 2GB range of call
      instruction genereated by TCG and so the calls would go nowhere,
      leading to a segfault.
      
      Fix by specifying an address for the code_gen_buffer,
      hopefully free and nearby the helpers.
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      4cd31ad2
  26. 22 12月, 2010 1 次提交
  27. 11 12月, 2010 2 次提交
    • A
      Add endianness as io mem parameter · 2507c12a
      Alexander Graf 提交于
      As stated before, devices can be little, big or native endian. The
      target endianness is not of their concern, so we need to push things
      down a level.
      
      This patch adds a parameter to cpu_register_io_memory that allows a
      device to choose its endianness. For now, all devices simply choose
      native endian, because that's the same behavior as before.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      2507c12a
    • A
      exec: introduce endianness swapped mmio · dd310534
      Alexander Graf 提交于
      The way we're currently modeling mmio is too simplified. We assume that
      every device has the same endianness as the target CPU. In reality,
      most devices are little endian (all PCI and ISA ones I'm aware of). Some
      are big endian (special system devices) and a very little fraction is
      target native endian (fw_cfg).
      
      So instead of assuming every device to be native endianness, let's move
      to a model where the device tells us which endianness it's in.
      
      That way we can compile the devices only once and get rid of all the ugly
      swap will be done by the underlying layer.
      
      For the same of readability, this patch only introduces the helper framework
      but doesn't allow the registering code to set its endianness yet.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      dd310534