1. 07 6月, 2017 26 次提交
  2. 06 6月, 2017 1 次提交
  3. 13 5月, 2017 7 次提交
  4. 11 1月, 2017 2 次提交
  5. 21 12月, 2016 1 次提交
    • T
      Move target-* CPU file into a target/ folder · fcf5ef2a
      Thomas Huth 提交于
      We've currently got 18 architectures in QEMU, and thus 18 target-xxx
      folders in the root folder of the QEMU source tree. More architectures
      (e.g. RISC-V, AVR) are likely to be included soon, too, so the main
      folder of the QEMU sources slowly gets quite overcrowded with the
      target-xxx folders.
      To disburden the main folder a little bit, let's move the target-xxx
      folders into a dedicated target/ folder, so that target-xxx/ simply
      becomes target/xxx/ instead.
      
      Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
      Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
      Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
      Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
      Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
      Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
      Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
      Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
      Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
      Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
      Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
      Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      fcf5ef2a
  6. 02 11月, 2016 1 次提交
    • R
      log: Add locking to large logging blocks · 1ee73216
      Richard Henderson 提交于
      Reuse the existing locking provided by stdio to keep in_asm, cpu,
      op, op_opt, op_ind, and out_asm as contiguous blocks.
      
      While it isn't possible to interleave e.g. in_asm or op_opt logs
      because of the TB lock protecting all code generation, it is
      possible to interleave cpu logs, or to interleave a cpu dump with
      an out_asm dump.
      
      For mingw32, we appear to have no viable solution for this.  The locking
      functions are not properly exported from the system runtime library.
      Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      1ee73216
  7. 24 6月, 2016 1 次提交
    • A
      softfloat: Implement run-time-configurable meaning of signaling NaN bit · af39bc8c
      Aleksandar Markovic 提交于
      This patch modifies SoftFloat library so that it can be configured in
      run-time in relation to the meaning of signaling NaN bit, while, at the
      same time, strictly preserving its behavior on all existing platforms.
      
      Background:
      
      In floating-point calculations, there is a need for denoting undefined or
      unrepresentable values. This is achieved by defining certain floating-point
      numerical values to be NaNs (which stands for "not a number"). For additional
      reasons, virtually all modern floating-point unit implementations use two
      kinds of NaNs: quiet and signaling. The binary representations of these two
      kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
      the first bit of mantissa).
      
      Up to 2008, standards for floating-point did not specify all details about
      binary representation of NaNs. More specifically, the meaning of the bit
      that is used for distinguishing between signaling and quiet NaNs was not
      strictly prescribed. (IEEE 754-2008 was the first floating-point standard
      that defined that meaning clearly, see [1], p. 35) As a result, different
      platforms took different approaches, and that presented considerable
      challenge for multi-platform emulators like QEMU.
      
      Mips platform represents the most complex case among QEMU-supported
      platforms regarding signaling NaN bit. Up to the Release 6 of Mips
      architecture, "1" in signaling NaN bit denoted signaling NaN, which is
      opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
      adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
      that, Mips architecture for SIMD (also known as MSA, or vector instructions)
      also specifies signaling bit in accordance to IEEE standard. MSA unit can be
      implemented with both pre-Release 6 and Release 6 main processor units.
      
      QEMU uses SoftFloat library to implement various floating-point-related
      instructions on all platforms. The current QEMU implementation allows for
      defining meaning of signaling NaN bit during build time, and is implemented
      via preprocessor macro called SNAN_BIT_IS_ONE.
      
      On the other hand, the change in this patch enables SoftFloat library to be
      configured in run-time. This configuration is meant to occur during CPU
      initialization, at the moment when it is definitely known what desired
      behavior for particular CPU (or any additional FPUs) is.
      
      The change is implemented so that it is consistent with existing
      implementation of similar cases. This means that structure float_status is
      used for passing the information about desired signaling NaN bit on each
      invocation of SoftFloat functions. The additional field in float_status is
      called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
      
      IMPORTANT:
      
      This change is not meant to create any change in emulator behavior or
      functionality on any platform. It just provides the means for SoftFloat
      library to be used in a more flexible way - in other words, it will just
      prepare SoftFloat library for usage related to Mips platform and its
      specifics regarding signaling bit meaning, which is done in some of
      subsequent patches from this series.
      
      Further break down of changes:
      
        1) Added field snan_bit_is_one to the structure float_status, and
           correspondent setter function set_snan_bit_is_one().
      
        2) Constants <float16|float32|float64|floatx80|float128>_default_nan
           (used both internally and externally) converted to functions
           <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
           This is necessary since they are dependent on signaling bit meaning.
           At the same time, for the sake of code cleanup and simplicity, constants
           <floatx80|float128>_default_nan_<low|high> (used only internally within
           SoftFloat library) are removed, as not needed.
      
        3) Added a float_status* argument to SoftFloat library functions
           XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
           XXX_maybe_silence_nan(XXX a_). This argument must be present in
           order to enable correct invocation of new version of functions
           XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
           here)
      
        4) Updated code for all platforms to reflect changes in SoftFloat library.
           This change is twofolds: it includes modifications of SoftFloat library
           functions invocations, and an addition of invocation of function
           set_snan_bit_is_one() during CPU initialization, with arguments that
           are appropriate for each particular platform. It was established that
           all platforms zero their main CPU data structures, so snan_bit_is_one(0)
           in appropriate places is not added, as it is not needed.
      
      [1] "IEEE Standard for Floating-Point Arithmetic",
          IEEE Computer Society, August 29, 2008.
      Signed-off-by: NThomas Schwinge <thomas@codesourcery.com>
      Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com>
      Signed-off-by: NAleksandar Markovic <aleksandar.markovic@imgtec.com>
      Tested-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
      Tested-by: NLeon Alrae <leon.alrae@imgtec.com>
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      [leon.alrae@imgtec.com:
       * cherry-picked 2 chunks from patch #2 to fix compilation warnings]
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      af39bc8c
  8. 20 6月, 2016 1 次提交