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  1. 28 2月, 2013 1 次提交
  3. 20 2月, 2013 2 次提交
  5. 19 2月, 2013 4 次提交
  7. 19 12月, 2012 1 次提交
  9. 28 10月, 2012 1 次提交
  11. 01 10月, 2012 1 次提交
    • H
      x86: Implement SMEP and SMAP · a9321a4d
      由 H. Peter Anvin 提交于 
      This patch implements Supervisor Mode Execution Prevention (SMEP) and
Supervisor Mode Access Prevention (SMAP) for x86.  The purpose of the
patch, obviously, is to help kernel developers debug the support for
those features.

A fair bit of the code relates to the handling of CPUID features.  The
CPUID code probably would get greatly simplified if all the feature
bit words were unified into a single vector object, but in the
interest of producing a minimal patch for SMEP/SMAP, and because I had
very limited time for this project, I followed the existing style.

[ v2: don't change the definition of the qemu64 CPU shorthand, since
  that breaks loading old snapshots.  Per Anthony Liguori this can be
  fixed once the CPU feature set is snapshot.

  Change the coding style slightly to conform to checkpatch.pl. ]
Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a9321a4d
  13. 15 8月, 2012 8 次提交
  15. 29 6月, 2012 1 次提交
    • B
      x86: avoid AREG0 for exceptions · 77b2bc2c
      由 Blue Swirl 提交于 
      Add an explicit CPUX86State parameter instead of relying on AREG0.

Merge raise_exception_env() to raise_exception(), likewise with
raise_exception_err_env() and raise_exception_err().

Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
as wrappers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      77b2bc2c
  17. 11 1月, 2012 1 次提交
    • A
      target-i386: fix SSE rounding and flush to zero · 2355c16e
      由 Aurelien Jarno 提交于 
      SSE rounding and flush to zero control has never been implemented. However
given that softfloat-native was using a single state for FPU and SSE and
given that glibc is setting both FPU and SSE state in fesetround(), this
was working correctly up to the switch to softfloat.

Fix that by adding an update_sse_status() function similar to
update_fpu_status(), and callin git on write to mxcsr.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      2355c16e
  19. 23 10月, 2009 1 次提交
  21. 04 10月, 2009 1 次提交
    • A
      target-i386: add RDTSCP support · 1b050077
      由 Andre Przywara 提交于 
      RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).
Signed-off-by: NAndre Przywara <andre.przywara@amd.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      1b050077
  23. 22 5月, 2009 1 次提交
  25. 17 11月, 2008 1 次提交
  27. 26 9月, 2008 1 次提交
  29. 30 8月, 2008 1 次提交
  31. 18 6月, 2008 1 次提交
  33. 05 6月, 2008 1 次提交
  35. 04 6月, 2008 1 次提交
  37. 29 5月, 2008 1 次提交
  39. 23 5月, 2008 1 次提交
  41. 22 5月, 2008 3 次提交
  43. 21 5月, 2008 1 次提交
  45. 18 5月, 2008 1 次提交
  47. 17 5月, 2008 1 次提交
  49. 16 5月, 2008 1 次提交
  51. 13 5月, 2008 2 次提交