- 01 2月, 2019 10 次提交
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由 Remi Denis-Courmont 提交于
A flawed test lead to the instructions always being treated as unallocated encodings. Fixes: https://bugs.launchpad.net/bugs/1813460Signed-off-by: NRemi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In disas_simd_indexed(), for the case of "complex fp", each indexable element is a complex pair, so the total size is twice that indicated in the 'size' field in the encoding. We were trying to do this "double the size" operation with a left shift by 1, but this is incorrect because the 'size' field is a MO_8/MO_16/MO_32/MO_64 value, and doubling the size should be done by a simple increment. This meant we were mishandling FCMLA (by element) of values where the real and imaginary parts are 32-bit floats, and would incorrectly UNDEF this encoding. (No other insns take this code path, and for 16-bit floats it happens that 1 << 1 and 1 + 1 are both the same). Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The FCMLA (by element) instruction exists in the "vector x indexed element" encoding group, but not in the "scalar x indexed element" group. Correctly UNDEF the unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-2-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD scalar x indexed element and vector x indexed element encoding group, the SDOT and UDOT instructions are vector only, and their opcode is unallocated in the scalar group. Correctly UNDEF this unallocated encoding. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-8-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the encoding groups * floating-point data-processing (1 source) * floating-point data-processing (2 source) * floating-point data-processing (3 source) * floating-point immediate * floating-point compare * floating-ponit conditional compare * floating-point conditional select bit 31 is M and bit 29 is S (and bit 30 is 0, already checked at this point in the decode). None of these groups allocate any encoding for M=1 or S=1. We checked this in disas_fp_compare(), disas_fp_ccomp() and disas_fp_csel(), but missed it in disas_fp_1src(), disas_fp_2src(), disas_fp_3src() and disas_fp_imm(). We also missed that in the fp immediate encoding the imm5 field must be all zeroes. Correctly UNDEF the unallocated encodings here. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-7-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the "add/subtract (extended register)" encoding group, the "opt" field in bits [23:22] must be zero. Correctly UNDEF the unallocated encodings where this field is not zero. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD load/store single structure encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Bit 31 must also be zero (a check we got right in ldst_multiple but not here). Correctly UNDEF these unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD load/store multiple structures encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Correctly UNDEF the currently unallocated encodings which have non-zeroes in those bits. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The PRFM prefetch insn in the load/store with imm9 encodings requires idx field 0b00; we were underdecoding this by only checking !is_unpriv (which is equivalent to idx != 2). Correctly UNDEF the unallocated encodings where idx == 0b01 and 0b11 as well as 0b10. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The "system instructions" and "system register move" subcategories of "branches, exception generating and system instructions" for A64 only apply if bits [23:22] are zero; other values are currently unallocated. Correctly UNDEF these unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-2-peter.maydell@linaro.org
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- 21 1月, 2019 11 次提交
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由 Richard Henderson 提交于
We can perform this with fewer operations. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-32-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-20-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-15-richard.henderson@linaro.org [fixed trivial comment nit] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-14-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This will enable PAuth decode in a subsequent patch. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-13-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-12-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-10-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-9-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Now properly signals unallocated for REV64 with SF=0. Allows for the opcode2 field to be decoded shortly. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-8-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-7-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-4-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 1月, 2019 1 次提交
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由 Richard Henderson 提交于
Use "register" TBFLAG_ANY to indicate shared state between A32 and A64, and "registers" TBFLAG_A32 & TBFLAG_A64 for fields that are specific to the given cpu state. Move ARM_TBFLAG_BE_DATA to shared state, instead of its current placement within "Bit usage when in AArch32 state". Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181218164348.7127-1-richard.henderson@linaro.org [PMM: removed the renaming of BE_DATA flag to BE] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 12月, 2018 1 次提交
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由 Richard Henderson 提交于
Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181210150501.7990-4-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 11月, 2018 1 次提交
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由 Peter Maydell 提交于
In handle_vec_simd_shli() we have a check: if (size > 3 && !is_q) { unallocated_encoding(s); return; } However this can never be true, because we calculate int size = 32 - clz32(immh) - 1; where immh is a 4 bit field which we know cannot be all-zeroes. So the clz32() return must be in {28,29,30,31} and the resulting size is in {0,1,2,3}, and "size > 3" is never true. This unnecessary code confuses Coverity's analysis: in CID 1396476 it thinks we might later index off the end of an array because the condition implies that we might have a size > 3. Remove the code, and instead assert that the size is in [0..3], since the decode that enforces that is somewhat distant from this function. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Tested-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 20181030162517.21816-1-peter.maydell@linaro.org
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- 24 10月, 2018 12 次提交
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由 Richard Henderson 提交于
Move cmtst_op expanders from translate-a64.c. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-17-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Move mla_op and mls_op expanders from translate-a64.c. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-16-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Move shi_op and sli_op expanders from translate-a64.c. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-15-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Move ssra_op and usra_op expanders from translate-a64.c. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-14-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Move expanders for VBSL, VBIT, and VBIF from translate-a64.c. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-9-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
For a sequence of loads or stores from a single register, little-endian operations can be promoted to an 8-byte op. This can reduce the number of operations by a factor of 8. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-5-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-4-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This is done generically in translator_loop. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181011205206.3552-3-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This can reduce the number of opcodes required for certain complex forms of load-multiple (e.g. ld4.16b). Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-id: 20181011205206.3552-2-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-9-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-8-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Most of the v8 extensions are self-contained within the ISAR registers and are not implied by other feature bits, which makes them the easiest to convert. Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-4-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 10月, 2018 1 次提交
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由 Richard Henderson 提交于
Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 08 10月, 2018 1 次提交
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由 Richard Henderson 提交于
Use the existing helpers to determine if (1) the fpu is enabled, (2) sve state is enabled, and (3) the current sve vector length. Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-6-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 8月, 2018 2 次提交
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由 Richard Henderson 提交于
These insns require u=1; failed to include that in the switch cases. This probably happened during one of the rebases just before final commit. Fixes: d17b7cdcSigned-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-6-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Also fold the FPCR/FPSR state onto the same line as PSTATE, and mention but do not dump disabled FPU state. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Tested-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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