- 05 3月, 2014 40 次提交
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由 Tom Musta 提交于
This patch adds a flag for the floating point conversion instructions introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are refactored to use this macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the byte and halfword variants of the Load and Reserve instructions. Since there is much commonality among all forms of Load and Reserve, a macro is provided and the existing implementations of lwarx and ldarx are refactoried to use this macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch addes the Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the non-signalling scalar conversion instructions: - VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision Non-Signalling (xscvdpspn) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Round to Single Precision (xsrsp) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Floating Merge Even Word (fmrgew) and Floating Merge Odd Word (fmrgow) instructions. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz) and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These instructions are unusual in that they are considered a floating point instruction if the indexed VSR is in the first half of the array (0-31) but they are considered vector instructions if the indexed VSR is in the second half of the array (32-63). Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patchs adds the VSX Logical instructions that are new with ISA V2.07: - VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword to Floating Point Format and Round to Single Precision (xscvuxdsp) and VSX Scalar Convert Signed Integer Douglbeword to Floating Point Format and Round to Single Precision (xscvsxdsp) instructions. The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP) is modified to support the rounding of the intermediate floating point result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Single Precision VSX Scalar Fused Multiply-Add instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp. The existing VSX_MADD() macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Reciprocal Square Root Estimate Single Precision (xsrsqrtesp) instruction. The existing VSX_RSQRTE() macro is modified to support rounding of the intermediate double-precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp) instruction. The existing VSX_SQRT() macro is modified to support rounding of the intermediate double-precision result to single-precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Reciprocal Estimate Single Precision (xsresp) instruction. The existing VSX_RE macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Divide Single Precision (xsdivsp) instruction. The existing VSX_DIV macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp) instruction. The existing VSX_MUL macro is modified to support rounding of the intermediate result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and VSX Scalar Subtract Single-Precision (xssubsp) instructions. The existing VSX_ADD_SUB macro is modified to support the rounding of the (intermediate) result to single-precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds two store scalar instructions: - Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch refactors the stxsdx instruction. Reusable code is extracted into a macro which will be used in subsequent patches in this series. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the scalar load instructions introduced in ISA V2.07: - Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax) - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx) - Load VSX Scalar Single-Precision Indexed (lxsspx) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch refactors the lxsdx generator. Resuable code is isolated into a macro. The macro will be used in subsequent patches in this series to implement other scalar load instructions. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag to identify those VSX instructions that are new to Power ISA V2.07. The flag is added to the Power 8 processor initialization so that the P8 models understand how to decode and emulate instructions in this category. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Round to Floating Point Integer instructions: - xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Integer Conversion instructions defined by V2.06 of the PowerPC ISA: - xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws - xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws - xscvsxddp, xscvuxddp - xvcvsxddp, xscvsxwdp, xvcvuxddp, xvcvuxwdp - xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX instructions that convert between floating point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point compare vector instructions: - xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.] - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.] Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point maximum and minimum instructions: - xsmaxdp, xvmaxdp, xvmaxsp - xsmindp, xvmindp, xvminsp Because of the Power ISA definitions of maximum and minimum on various boundary cases, the standard softfloat comparison routines (e.g. float64_lt) do not work as well as one might think. Therefore specific routines for comparing 64 and 32 bit floating point numbers are implemented in the PowerPC helper code. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX scalar floating point compare ordered and unordered instructions. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point multiply/add instructions defined by V2.06 of the PowerPC ISA: - xsmaddadp, xvmaddadp, xvmaddasp - xsmaddmdp, xvmaddmdp, xvmaddmsp - xsmsubadp, xvmsubadp, xvmsubasp - xsmsubmdp, xvmsubmdp, xvmsubmsp - xsnmaddadp, xvnmaddadp, xvnmaddasp - xsnmaddmdp, xvnmaddmdp, xvnmaddmsp - xsnmsubadp, xvnmsubadp, xvnmsubasp - xsnmsubmdp, xvnmsubmdp, xvnmsubmsp Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point test for software square root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp, xvtsqrtdp, xvtsqrtsp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point test for software divide instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp, and xvtdivsp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point reciprocal square root estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp, xvrsqrtedp, xvrsqrtesp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point square root instructions defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX floating point reciprocal estimate instructions defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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