1. 07 11月, 2018 1 次提交
  2. 03 10月, 2018 2 次提交
  3. 24 8月, 2018 2 次提交
    • A
      target-i386: fix segment limit check in ljmp · db7196db
      Andrew Oates 提交于
      The current implementation has three bugs,
       * segment limits are not enforced in protected mode if the L bit is set
         in the target segment descriptor
       * segment limits are not enforced in compatibility mode (ljmp to 32-bit
         code segment in long mode)
       * #GP(new_cs) is generated rather than #GP(0)
      
      Now the segment limits are enforced if we're not in long mode OR the
      target code segment doesn't have the L bit set.
      Signed-off-by: NAndrew Oates <aoates@google.com>
      Message-Id: <20180816011903.39816-1-andrew@andrewoates.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      db7196db
    • A
      target-i386: Fix lcall/ljmp to call gate in IA-32e mode · 0aca0605
      Andrew Oates 提交于
      Currently call gates are always treated as 32-bit gates.  In IA-32e mode
      (either compatibility or 64-bit submode), system segment descriptors are
      always 64-bit.  Treating them as 32-bit has the expected unfortunate
      effect: only the lower 32 bits of the offset are loaded, the stack
      pointer is truncated, a bad new stack pointer is loaded from the TSS (if
      switching privilege levels), etc.
      
      This change adds support for 64-bit call gate to the lcall and ljmp
      instructions.  Additionally, there should be a check for non-canonical
      stack pointers, but I've omitted that since there doesn't seem to be
      checks for non-canonical addresses in this code elsewhere.
      
      I've left the raise_exception_err_ra lines unwapped at 80 columns to
      match the style in the rest of the file.
      Signed-off-by: NAndrew Oates <aoates@google.com>
      Message-Id: <20180819181725.34098-1-andrew@andrewoates.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      0aca0605
  4. 29 6月, 2018 1 次提交
  5. 04 7月, 2017 2 次提交
    • P
      target/i386: simplify handling of conforming code segments on interrupt · 1110bfe6
      Paolo Bonzini 提交于
      Move the handling of conforming code segments before the handling
      of stack switch.
      
      Because dpl == cpl after the new "if", it's now unnecessary to check
      the C bit when testing dpl < cpl.  Furthermore, dpl > cpl is checked
      slightly above the modified code, so the final "else" is unreachable
      and we can remove it.
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      1110bfe6
    • W
      target/i386: fix interrupt CPL error when using ist in x86-64 · e95e9b88
      Wu Xiang 提交于
      In do_interrupt64(), when interrupt stack table(ist) is enabled
      and the the target code segment is conforming(e2 & DESC_C_MASK), the
      old implementation always set new CPL to 0, and SS.RPL to 0.
      
      This is incorrect for when CPL3 code access a CPL0 conforming code
      segment, the CPL should remain unchanged. Otherwise higher privileged
      code can be compromised.
      
      The patch fix this for always set dpl = cpl when the target code segment
      is conforming, and modify the last parameter `flags`, which contains
      correct new CPL, in cpu_x86_load_seg_cache().
      Signed-off-by: NWu Xiang <willx8@gmail.com>
      Message-Id: <20170621142152.GA18094@wxdeubuntu.ipads-lab.se.sjtu.edu.cn>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e95e9b88
  6. 09 3月, 2017 1 次提交
  7. 17 2月, 2017 1 次提交
  8. 28 1月, 2017 1 次提交
  9. 21 12月, 2016 1 次提交
    • T
      Move target-* CPU file into a target/ folder · fcf5ef2a
      Thomas Huth 提交于
      We've currently got 18 architectures in QEMU, and thus 18 target-xxx
      folders in the root folder of the QEMU source tree. More architectures
      (e.g. RISC-V, AVR) are likely to be included soon, too, so the main
      folder of the QEMU sources slowly gets quite overcrowded with the
      target-xxx folders.
      To disburden the main folder a little bit, let's move the target-xxx
      folders into a dedicated target/ folder, so that target-xxx/ simply
      becomes target/xxx/ instead.
      
      Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
      Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
      Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
      Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
      Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
      Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
      Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
      Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
      Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
      Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
      Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
      Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      fcf5ef2a
  10. 15 9月, 2016 1 次提交
    • S
      target-i386: Fixed syscall posssible segfault · 885b7c44
      Stanislav Shmarov 提交于
      In user-mode emulation env->idt.base memory is
      allocated in linux-user/main.c with
      size 8*512 = 4096 (for 64-bit).
      When fake interrupt EXCP_SYSCALL is thrown
      do_interrupt_user checks destination privilege level
      for this fake exception, and tries to read 4 bytes
      at address base + (256 * 2^4)=4096, that causes
      segfault.
      
      Privlege level was checked only for int's, so lets
      read dpl from memory only for this case.
      Signed-off-by: NStanislav Shmarov <snarpix@gmail.com>
      Message-Id: <1473773008-2588376-1-git-send-email-snarpix@gmail.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      885b7c44
  11. 09 6月, 2016 1 次提交
  12. 19 5月, 2016 1 次提交
  13. 09 2月, 2016 1 次提交
  14. 03 2月, 2016 1 次提交
  15. 29 1月, 2016 1 次提交
    • P
      x86: Clean up includes · b6a0aa05
      Peter Maydell 提交于
      Clean up includes so that osdep.h is included first and headers
      which it implies are not included manually.
      
      This commit was created with scripts/clean-includes.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1453832250-766-11-git-send-email-peter.maydell@linaro.org
      b6a0aa05
  16. 23 10月, 2015 1 次提交
  17. 25 9月, 2015 1 次提交
  18. 16 9月, 2015 1 次提交
  19. 05 6月, 2015 1 次提交
  20. 10 3月, 2015 1 次提交
    • B
      x86: fix SS selector in SYSRET · ac576229
      Bill Paul 提交于
      According to my reading of the Intel documentation, the SYSRET instruction
      is supposed to force the RPL bits of the %ss register to 3 when returning
      to user mode. The actual sequence is:
      
      SS.Selector <-- (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *)
      
      However, the code in helper_sysret() leaves them at 0 (in other words, the "OR
      3" part of the above sequence is missing). It does set the privilege level
      bits of %cs correctly though.
      
      This has caused me trouble with some of my VxWorks development: code that runs
      okay on real hardware will crash on QEMU, unless I apply the patch below.
      Signed-off-by: NBill Paul <wpaul@windriver.com>
      Message-Id: <201503091548.01462.wpaul@windriver.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      ac576229
  21. 20 1月, 2015 1 次提交
  22. 12 11月, 2014 1 次提交
  23. 26 9月, 2014 1 次提交
  24. 22 8月, 2014 1 次提交
  25. 05 6月, 2014 3 次提交
  26. 29 5月, 2014 1 次提交
  27. 22 5月, 2014 4 次提交
  28. 13 5月, 2014 2 次提交
  29. 14 3月, 2014 3 次提交