- 05 3月, 2014 40 次提交
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由 Alexey Kardashevskiy 提交于
The existing load_elf() just returns -1 if it fails to load ELF. However it could be smarter than this and tell more about the failure such as wrong endianness or incompatible platform. This adds additional return codes for wrong architecture, wrong endianness and if the image is not ELF at all. This adds a load_elf_strerror() helper to convert return codes into string messages. This fixes handling of what load_elf() returns for s390x, other callers just check the return value for <0 and this remains unchanged. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
At the moment in the case of error, load_elf() returns -1 so load_kernel() will not signal error at all. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
Currently everybody uses ELF kernel images with "-kernel" option on pseries machine but QEMU still tries to boot from an image even it fails to recognize it is ELF. This produces undefined behaviour if the user tries a kernel image compiled for another architecture. This removes support of raw kernel images. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Fabien Chouteau 提交于
This implementation doesn't include ring priority, TCP/IP Off-Load, QoS. Signed-off-by: NFabien Chouteau <chouteau@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
PR KVM lacks support of many SPRs in set/get one register API but it does really break PR KVM. So convert them to switchable traces for now. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Edgar E. Iglesias 提交于
Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> [agraf: fix up stray quotes and newlines in strings] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
When ppc_store_slb() is called from kvm_arch_get_registers(), it stores a SLB in CPUPPCState::slb[slot]. However it drops the slot number from ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not have correct "index" field anymore. This broke migration with LPCR_AIR enabled as now the guest is handling interrupts in virtual mode and unable to reconstruct correct SLBs anymore. This adds "index" field for valid SLBs when putting them to KVM. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: qemu-stable@nongnu.org Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Load Floating Point as Integer Word and Zero Indexed (lfiwzx) instruction which was introduced in Power ISA 2.06. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
The frsqrtes instruction was introduced prior to ISA 2.06 and is support on both the Power7 and Power8 processors. However, this instruction is handled as illegal in the current QEMU emulation machines. This patch enables the existing implemention of frsqrtes in the P7 and P8 machines. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Floating Point Test for Divide instruction which was introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for Floating Point Test instructions that were introduced in Power ISA V2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
The fri* series of instructions was introduced prior to ISA 2.06 and is supported on Power7 and Power8 hardware. However, the instruction is still considered illegal in the P7 and P8 QEMU emulation models. This patch enables these instructions for the P7 and P8 machines. Also, the existing helper is modified to correctly handle some of the boundary cases (NaNs and the inexact flag). Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the fcfids, fcfidu and fcfidus instructions which were introduced in Power ISA 2.06B. A common macro is provided to eliminate repetitious code, and the existing fcfid instruction is refactored to use this macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the four floating point to integer conversion instructions introduced by Power ISA V2.06: - Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward Zero (fctiwuz) - Floating Convert to Integer Doubleword Unsigned (fctidu) - Floating Convert to Integer Doubleword Unsigned with Round Toward Zero (fctiduz) A common macro is developed to eliminate repetitious code. Existing instructions are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz). Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for the floating point conversion instructions introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are refactored to use this macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the byte and halfword variants of the Load and Reserve instructions. Since there is much commonality among all forms of Load and Reserve, a macro is provided and the existing implementations of lwarx and ldarx are refactoried to use this macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch addes the Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the non-signalling scalar conversion instructions: - VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision Non-Signalling (xscvdpspn) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Round to Single Precision (xsrsp) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Floating Merge Even Word (fmrgew) and Floating Merge Odd Word (fmrgow) instructions. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz) and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These instructions are unusual in that they are considered a floating point instruction if the indexed VSR is in the first half of the array (0-31) but they are considered vector instructions if the indexed VSR is in the second half of the array (32-63). Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patchs adds the VSX Logical instructions that are new with ISA V2.07: - VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword to Floating Point Format and Round to Single Precision (xscvuxdsp) and VSX Scalar Convert Signed Integer Douglbeword to Floating Point Format and Round to Single Precision (xscvsxdsp) instructions. The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP) is modified to support the rounding of the intermediate floating point result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Single Precision VSX Scalar Fused Multiply-Add instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp. The existing VSX_MADD() macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Reciprocal Square Root Estimate Single Precision (xsrsqrtesp) instruction. The existing VSX_RSQRTE() macro is modified to support rounding of the intermediate double-precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp) instruction. The existing VSX_SQRT() macro is modified to support rounding of the intermediate double-precision result to single-precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Reciprocal Estimate Single Precision (xsresp) instruction. The existing VSX_RE macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Divide Single Precision (xsdivsp) instruction. The existing VSX_DIV macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp) instruction. The existing VSX_MUL macro is modified to support rounding of the intermediate result to single precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and VSX Scalar Subtract Single-Precision (xssubsp) instructions. The existing VSX_ADD_SUB macro is modified to support the rounding of the (intermediate) result to single-precision. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds two store scalar instructions: - Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch refactors the stxsdx instruction. Reusable code is extracted into a macro which will be used in subsequent patches in this series. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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