- 19 5月, 2015 11 次提交
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由 Gonglei 提交于
Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gonglei 提交于
Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gonglei 提交于
QOMify pci-cirrus-vga like isa-cirrus-vga device. Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Peter Maydell 提交于
target-arm: * New board model: xlnx-ep108 * Some more preparation for AArch64 EL2/EL3 * Fix bugs in access checking for generic counter registers * Remove a stray '+' sign # gpg: Signature made Mon May 18 20:13:05 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150518-3: (21 commits) target-arm: Remove unneeded '+' target-arm: Correct accessfn for CNTV_TVAL_EL0 target-arm: Correct accessfn for CNTP_{CT}VAL_EL0 target-arm: Add WFx syndrome function target-arm: Add EL3 and EL2 TCR checking target-arm: Add TTBR regime function and use linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create arm: xlnx-ep108: Add bootloading arm: xlnx-ep108: Add external RAM arm: Add xlnx-ep108 machine arm: xlnx-zynqmp: Add UART support char: cadence_uart: Split state struct and type into header char: cadence_uart: Clean up variable names arm: xlnx-zynqmp: Add GEM support net: cadence_gem: Split state struct and type into header net: cadence_gem: Clean up variable names arm: xlnx-zynqmp: Connect CPU Timers to GIC arm: xlnx-zynqmp: Add GIC arm: Introduce Xilinx ZynqMP SoC target-arm: cpu64: Add support for Cortex-A53 ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1431499963-1019-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Bellows 提交于
Adds a utility function for creating a WFx exception syndrome Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-9-git-send-email-greg.bellows@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Bellows 提交于
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-8-git-send-email-greg.bellows@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Bellows 提交于
Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-7-git-send-email-greg.bellows@linaro.org [PMM: fixed regime_ttbr() return type to be uint64_t] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Timothy Baldwin 提交于
Misspelled system call name in macro was causing timerfd_create not to be supported for the ARM target. Signed-off-by: NTimothy Edward Baldwin <T.E.Baldwin99@members.leeds.ac.uk> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 5月, 2015 14 次提交
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由 Peter Crosthwaite 提交于
Add bootloader support using standard ARM bootloader. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a machine model for the Xilinx ZynqMP SoC EP108 board. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Create a new header for Cadence UART to allow using the device with modern SoC programming conventions. The state struct needs to be visible to embed the device in SoC containers. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 46a0fbd45b6b205f54c4a8c778deb75c77f8abdf.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Clean up some variable names in preparation for migrating the state struct and type cast macro to a public header. The acronym "UART" on it's own is not specific enough to be used in a more global namespace so preface with "cadence". Fix the capitalisation of "uart" in the state type while touching the typename. Preface macros used by the state struct itself with CADENCE_UART so they don't conflict in namespace either. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3812b7426c338beae9e082557f3524a99310ddc6.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Create a new header for Cadence GEM to allow using the device with modern SoC programming conventions. The state struct needs to be visible to embed the device in SoC containers. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a98b5df6440c5bff8f813a26bb53ce1cfefb4c4c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Cleanup some variable names in preparation for migrating the state struct and type cast macro to a public header. The acronym "GEM" on its own is not specific enough to be used in a more global namespace so preface with "cadence". Fix the capitalisation of "gem" in the state type while touching the typename. Also preface the GEM_MAXREG macro as this will need to migrate to public header. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 8e2b0687b3a7b7a3fde5ba2f3bee6f3b911e84ef.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Connect the GPIO outputs from the individual CPUs for the timers to the GIC. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add the ARM Cortex-A53 processor definition. Similar to A57, but with different L1 I cache policy, phys addr size and different cache geometries. The cache sizes is implementation configurable, but use these values (from Xilinx Zynq MPSoC) as a default until cache size configurability is added. Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Rename some A57 CP register variables in preparation for support for Cortex A53. Use "a57_a53" to describe the shareable features. Some of the CP15 registers (such as ACTLR) are specific to implementation, but we currently just RAZ them so continue with that as the policy for both A57 and A53 processors under a shared definition. Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5a5f957994677d91435190b3be1cefa6f657e274.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 5月, 2015 1 次提交
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由 Peter Maydell 提交于
qapi: Fix qapi mangling of downstream names, and more # gpg: Signature made Fri May 15 17:41:31 2015 BST using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-qapi-2015-05-15: (26 commits) qapi: Inline gen_command_decl_prologue(), gen_command_def_prologue() qapi: Drop pointless flush() before close() qapi: Factor open_output(), close_output() out of generators qapi: Turn generators' mandatory option -i into an argument qapi: Fix generators to report command line errors decently qapi: Factor parse_command_line() out of the generators qapi: qapi-commands.py option --type is unused, drop it qapi: qapi-event.py option -b does nothing, drop it tests: Add missing dependencies on $(qapi-py) qapi: Support downstream events and commands qapi: Support downstream alternates qapi: Support downstream flat unions qapi: Support downstream simple unions qapi: Support downstream structs qapi: Support downstream enums qapi: Make c_type() consistently convert qapi names qapi: Tidy c_type() logic qapi: Move camel_to_upper(), c_enum_const() to closely related code qapi: Use c_enum_const() in generate_alternate_qtypes() qapi: Simplify c_enum_const() ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 15 5月, 2015 14 次提交
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由 Peter Maydell 提交于
Per-memop alignment # gpg: Signature made Thu May 14 20:17:27 2015 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20150514: tcg: Add MO_ALIGN, MO_UNALN tcg: Push merged memop+mmu_idx parameter to softmmu routines tcg: Merge memop and mmu_idx parameters to qemu_ld/st Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
These modifiers control, on a per-memory-op basis, whether unaligned memory accesses are allowed. The default setting reflects the target's definition of ALIGNED_ONLY. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Mandatory option is silly, and the error handling is missing: the programs crash when -i isn't supplied. Make it an argument, and check it properly. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Report to stderr, prefix with the program name. Also reject extra arguments. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Anything but --type sync (which is the default) suppresses output entirely, which makes no sense. Dates back to the initial commit c17d9908. Commit message says "Currently only generators for synchronous qapi/qmp functions are supported", so maybe output other than "synchronous qapi/qmp" was planned at the time, to be selected with --type. Should other kinds of output ever materialize, we can put the option back. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Eric Blake 提交于
Enhance the testsuite to cover downstream events and commands. Events worked without more tweaks, but commands needed a few final updates in the generator to mangle names in the appropriate places. In making those tweaks, it was easier to drop type_visitor() and inline its actions instead. Signed-off-by: NEric Blake <eblake@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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