1. 19 12月, 2012 3 次提交
  2. 16 12月, 2012 1 次提交
  3. 14 12月, 2012 1 次提交
    • D
      target-ppc: Don't use hwaddr to represent hardware state · b162d02e
      David Gibson 提交于
      The hwaddr type is somewhat vaguely defined as being able to contain bus
      addresses on the widest possible bus in the system.  For that reason it's
      discouraged for representing specific pieces of persistent hardware state,
      which should instead use an explicit width type that matches the bits
      available in real hardware.  In particular, because of the possibility that
      the size of hwaddr might change if different buses are added to the target
      in future, it's not suitable for use in vm state descriptions for savevm
      and migration.
      
      This patch purges such unwise uses of hwaddr from the ppc target code,
      which turns out to be just one.  The ppcemb_tlb_t struct, used on a number
      of embedded ppc models to represent a TLB entry contains a hwaddr for the
      real address field.  This patch changes it to be a fixed uint64_t which is
      suitable enough for all machine types which use this structure.
      
      Other uses of hwaddr in CPUPPCState turn out not to be problematic:
      htab_base and htab_mask are just used for the convenience of the TCG code;
      the underlying machine state is the SDR1 register, which is stored with
      a suitable type already.  Likewise the mpic_cpu_base field is only used
      internally and does not represent fundamental hardware state which needs to
      be saved.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      b162d02e
  4. 08 12月, 2012 3 次提交
  5. 27 11月, 2012 1 次提交
    • J
      PPC: Fix missing TRACE exception · f0cc4aa8
      Julio Guerra 提交于
      This patch fixes bug 1031698 :
      https://bugs.launchpad.net/qemu/+bug/1031698
      
      If we look at the (truncated) translation of the conditional branch
      instruction in the test submitted in the bug post, the call to the
      exception helper is missing in the "bne-false" chunk of translated
      code :
      
      IN:
      bne-    0x1800278
      
      OUT:
      0xb544236d:  jne    0xb5442396
      
      0xb5442373:  mov    %ebp,(%esp)
      0xb5442376:  mov    $0x44,%ebx
      0xb544237b:  mov    %ebx,0x4(%esp)
      0xb544237f:  mov    $0x1800278,%ebx
      0xb5442384:  mov    %ebx,0x25c(%ebp)
      0xb544238a:  call   0x827475a
                           ^^^^^^^^^^^^^^^^^^
      
      0xb5442396:  mov    %ebp,(%esp)
      0xb5442399:  mov    $0x44,%ebx
      0xb544239e:  mov    %ebx,0x4(%esp)
      0xb54423a2:  mov    $0x1800270,%ebx
      0xb54423a7:  mov    %ebx,0x25c(%ebp)
      
      Indeed, gen_exception(ctx, excp) called by gen_goto_tb (called by
      gen_bcond) changes ctx->exception's value to excp's :
      
      gen_bcond()
      {
        gen_goto_tb(ctx, 0, ctx->nip + li - 4);
        /* ctx->exception value is POWERPC_EXCP_BRANCH */
      
        gen_goto_tb(ctx, 1, ctx->nip);
        /* ctx->exception now value is POWERPC_EXCP_TRACE */
      }
      
      Making the following gen_goto_tb()'s test false during the second call :
      
      if ((ctx->singlestep_enabled &
          (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
          ctx->exception == POWERPC_EXCP_BRANCH /* false...*/) {
               target_ulong tmp = ctx->nip;
               ctx->nip = dest;
               /* ... and this is the missing call */
               gen_exception(ctx, POWERPC_EXCP_TRACE);
               ctx->nip = tmp;
      }
      
      So the patch simply adds the missing matching case, fixing our problem.
      Signed-off-by: NJulio Guerra <guerr@julio.in>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f0cc4aa8
  6. 17 11月, 2012 2 次提交
  7. 10 11月, 2012 1 次提交
  8. 02 11月, 2012 2 次提交
  9. 01 11月, 2012 2 次提交
    • D
      target-ppc: Extend FPU state for newer POWER CPUs · 30304420
      David Gibson 提交于
      This patch adds some extra FPU state to CPUPPCState.  Specifically,
      fpscr is extended to a target_ulong bits, since some recent (64 bit)
      CPUs now have more status bits than fit inside 32 bits.  Also, we add
      the 32 VSR registers present on CPUs with VSX (these extend the
      standard FP regs, which together with the Altivec/VMX registers form a
      64 x 128bit register file for VSX).
      
      We don't actually support the instructions using these extra registers
      in TCG yet, but we still need a place to store the state so we can
      sync it with KVM and savevm/loadvm it.  This patch updates the savevm
      code to not fail on the extended state, but also does not actually
      save it - that's a project for another patch.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      30304420
    • D
      target-ppc: Rework storage of VPA registration state · ac7d12ba
      David Gibson 提交于
      We change the storage of the VPA information to explicitly use fixed
      size integer types which will make life easier for syncing this data with
      KVM, which we will need in future.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      [agraf: fix commit message]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      ac7d12ba
  10. 31 10月, 2012 6 次提交
  11. 29 10月, 2012 3 次提交
    • D
      target-ppc: Rework storage of VPA registration state · 1bfb37d1
      David Gibson 提交于
      With PAPR guests, hypercalls allow registration of the Virtual Processor
      Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow
      for certain communication between the guest and hypervisor.  Currently, we
      store the addresses of the three areas and the size of the dtl in
      CPUPPCState.
      
      The SLB shadow and DTL are variable sized, with the size being retrieved
      from within the registered memory area at the hypercall time.  This size
      can later be overwritten with other information, however, so we need to
      save the size as of registration time.  We already do this for the DTL,
      but not for the SLB shadow, so this patch fixes that.
      
      In addition, we change the storage of the VPA information to use fixed
      size integer types which will make life easier for syncing this data with
      KVM, which we will need in future.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      1bfb37d1
    • A
      PPC: 440: Emulate DCBR0 · e598a9c5
      Alexander Graf 提交于
      The DCBR0 register on 440 is used to implement system reset. The same
      register is used on 405 as well, so just reuse the code.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      e598a9c5
    • P
      Drop unnecessary check of TARGET_PHYS_ADDR_SPACE_BITS · 21b2f13a
      Peter Maydell 提交于
      For all our PPC targets the physical address space is at least
      36 bits, so drop an unnecessary preprocessor conditional check
      on TARGET_PHYS_ADDR_SPACE_BITS (erroneously introduced as part
      of the change from target_phys_addr_t to hwaddr). This brings
      this bit of code into line with the way we handle the other
      cases which were originally checking TARGET_PHYS_ADDR_BITS in
      order to avoid compiler complaints about overflowing a 32 bit type.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      21b2f13a
  12. 28 10月, 2012 1 次提交
  13. 23 10月, 2012 1 次提交
    • A
      Rename target_phys_addr_t to hwaddr · a8170e5e
      Avi Kivity 提交于
      target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
      reserved) and its purpose doesn't match the name (most target_phys_addr_t
      addresses are not target specific).  Replace it with a finger-friendly,
      standards conformant hwaddr.
      
      Outstanding patchsets can be fixed up with the command
      
        git rebase -i --exec 'find -name "*.[ch]"
                              | xargs s/target_phys_addr_t/hwaddr/g' origin
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a8170e5e
  14. 05 10月, 2012 4 次提交
  15. 04 10月, 2012 8 次提交
  16. 28 9月, 2012 1 次提交