- 19 1月, 2016 1 次提交
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由 Peter Maydell 提交于
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1449505425-32022-4-git-send-email-peter.maydell@linaro.org
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- 15 1月, 2016 2 次提交
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由 Shannon Zhao 提交于
When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. While UEFI can use libfdt to disable the RTC device node in the DTB that it passes to the OS, it cannot modify AML. Therefore, we won't generate the RTC ACPI device at all when using UEFI. Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NAndrew Jones <drjones@redhat.com> Message-id: 1452867091-4023-1-git-send-email-shannon.zhao@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 1月, 2016 7 次提交
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由 Markus Armbruster 提交于
Commit 6daf194d, be62a2eb and 312fd5f2 got rid of a bunch, but they keep coming back. Tracked down with the Coccinelle semantic patch from commit 312fd5f2. Cc: Fam Zheng <famz@redhat.com> Cc: Peter Crosthwaite <crosthwaitepeter@gmail.com> Cc: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Dominik Dingel <dingel@linux.vnet.ibm.com> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Jason J. Herne <jjherne@linux.vnet.ibm.com> Cc: Stefan Berger <stefanb@linux.vnet.ibm.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: Changchun Ouyang <changchun.ouyang@intel.com> Cc: zhanghailiang <zhang.zhanghailiang@huawei.com> Cc: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: NMarkus Armbruster <armbru@pond.sub.org> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: NCornelia Huck <cornelia.huck@de.ibm.com> Acked-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Acked-by: NFam Zheng <famz@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Message-Id: <1450452927-8346-17-git-send-email-armbru@redhat.com>
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由 Markus Armbruster 提交于
Done with this Coccinelle semantic patch @@ expression FMT, E, S; expression list ARGS; @@ - error_report(FMT, ARGS, error_get_pretty(E)); + error_reportf_err(E, FMT/*@@@*/, ARGS); ( - error_free(E); | exit(S); | abort(); ) followed by a replace of '%s"/*@@@*/' by '"' and some line rewrapping, because I can't figure out how to make Coccinelle transform strings. We now use the error whole instead of just its message obtained with error_get_pretty(). This avoids suppressing its hint (see commit 50b7b000), but I can't see how the errors touched in this commit could come with hints. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Message-Id: <1450452927-8346-12-git-send-email-armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Markus Armbruster 提交于
Same Coccinelle semantic patch as in commit 565f65d2. We now use the original error whole instead of just its message obtained with error_get_pretty(). This avoids suppressing its hint (see commit 50b7b000), but I don't think the errors touched in this commit can come with hints. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Message-Id: <1450452927-8346-3-git-send-email-armbru@redhat.com>
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由 Markus Armbruster 提交于
virt_set_gic_version() calls exit(1) when passed an invalid property value. Property setters are not supposed to do that. Screwed up in commit b92ad394. Harmless, because the property belongs to a machine. Set an error object instead. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-arm@nongnu.org Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Markus Armbruster 提交于
Printing CPU registers is not helpful during machine initialization. Moreover, these are straightforward configuration or "can get resources" errors, so dumping core isn't appropriate either. Replace hw_error() by error_report(); exit(1). Matches how we report these errors in other machine initializations. Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-arm@nongnu.org Cc: qemu-ppc@nongnu.org Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Signed-off-by: NMarkus Armbruster <armbru@pond.sub.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Message-Id: <1450370121-5768-2-git-send-email-armbru@redhat.com> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Markus Armbruster 提交于
Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Message-Id: <1449764955-10741-3-git-send-email-armbru@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Markus Armbruster 提交于
Done with this Coccinelle semantic patch: @@ type T; identifier FUN, RET; expression list ARGS; expression ERR, EC; @@ ( - T RET = FUN(ARGS, &ERR); + T RET = FUN(ARGS, &error_fatal); | - RET = FUN(ARGS, &ERR); + RET = FUN(ARGS, &error_fatal); | - FUN(ARGS, &ERR); + FUN(ARGS, &error_fatal); ) - if (ERR != NULL) { - error_report_err(ERR); - exit(EC); - } This is actually a more elegant version of my initial semantic patch by courtesy of Eduardo. It leaves dead Error * variables behind, cleaned up manually. Cc: qemu-arm@nongnu.org Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com>
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- 12 1月, 2016 1 次提交
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由 Ashok Kumar 提交于
Support the legacy -nic syntax for creating PCI network devices as well as the new-style -device options. This makes life easier for people moving from x86 KVM virtualization to ARM KVM virtualization and expecting their network configuration options to work the same way for both setups. We use "virtio" as the default NIC model if the user doesn't specify one. Signed-off-by: NAshok Kumar <ashoks@broadcom.com> Message-id: 1452091659-17698-1-git-send-email-ashoks@broadcom.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: expanded and clarified commit message] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 12月, 2015 3 次提交
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由 Igor Mammedov 提交于
Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Igor Mammedov 提交于
Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com>
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由 Xiao Guangrong 提交于
Let build_header() support specified OEM table id so that we can build multiple SSDT later If the oem table id is not specified (aka, NULL), we use the default id instead as the previous behavior Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Signed-off-by: NXiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 17 12月, 2015 10 次提交
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由 Jean-Christophe Dubois 提交于
With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add a gpio-keys node. This is used for Poweroff for the systems which use DT not ACPI. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Tested-by: NWei Huang <wei@redhat.com> Message-id: 1449804086-3464-11-git-send-email-zhaoshenglong@huawei.com [PMM: use "standard-headers/linux/input.h" rather than <linux/input.h>] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Currently mach-virt model doesn't support powerdown request. Guest VM doesn't react to system_powerdown from monitor console (or QMP) because there is no communication mechanism for such requests. This patch registers GPIO Pin 3 with powerdown notification. So guest VM can receive notification when such powerdown request is triggered. Signed-off-by: NWei Huang <wei@redhat.com> Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NWei Huang <wei@redhat.com> Tested-by: NWei Huang <wei@redhat.com> Message-id: 1449804086-3464-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Here GPIO pin 3 is used for Power Button, add _E03 in ACPI DSDT table. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Tested-by: NWei Huang <wei@redhat.com> Message-id: 1449804086-3464-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add power button device in ACPI DSDT table. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NWei Huang <wei@redhat.com> Tested-by: NWei Huang <wei@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-6-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add GPIO controller in ACPI DSDT table. It can be used for gpio event. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Tested-by: NWei Huang <wei@redhat.com> Message-id: 1449804086-3464-5-git-send-email-zhaoshenglong@huawei.com Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
ACPI 5.0 supports GPIO-signaled ACPI Events. This can be used for powerdown, hotplug evnets. Add a GPIO controller in machine virt, to support powerdown, maybe can be used for cpu hotplug. And here we use pl061. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NWei Huang <wei@redhat.com> Tested-by: NWei Huang <wei@redhat.com> Message-id: 1449804086-3464-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mammedov 提交于
ASL Interrupt() macro translates to Extended Interrupt Descriptor which supports variable number of IRQs. It will be used for conversion of ASL code for pc/q35 machines that use it for returning several IRQs in _PSR object. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Xiao Guangrong 提交于
Add serialized method support so that explicit Mutex can be avoided Signed-off-by: NXiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 15 12月, 2015 1 次提交
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由 Gabriel L. Somlo 提交于
Read callbacks are now only invoked at item selection, before any data is read. As such, the value of the offset argument passed to the callback will always be 0. Also, the two callback instances currently in use both leave their offset argument unused. This patch removes the offset argument from the fw_cfg read callback prototype, and from the currently available instances. The unused (write) callback prototype is also removed (write support was removed earlier, in commit 023e3148). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Marc Marí <markmb@redhat.com> Signed-off-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Message-id: 1446733972-1602-4-git-send-email-somlo@cmu.edu Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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- 24 11月, 2015 1 次提交
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由 Alistair Francis 提交于
The minimum RAM check logic for the Xiilnx EP108 was off by one, which caused a false positive. Correct the logic to only print warnings when the RAM is below 0x8000000. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: fba8112ca7b01efd72553332b8045ecf107b7662.1448021100.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 11月, 2015 1 次提交
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由 Guenter Roeck 提交于
Add support for the Xilinx XADC core used in Zynq 7000. References: - Zynq-7000 All Programmable SoC Technical Reference Manual - 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter Tested with Linux using QEMU machine xilinx-zynq-a9 with devicetree files zynq-zc702.dtb and zynq-zc706.dtb, and kernel configuration multi_v7_defconfig. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> [ PC changes: * Changed macro names to match TRM where possible * Made programmers model macro scheme consistent * Dropped XADC_ZYNQ_ prefix on local macros * Fix ALM field width * Update threshold-comparison interrupts in _update_ints() * factored out DFIFO pushes into helper. Renamed to "push/pop" * Changed xadc_reg to 10 bits and added OOB check. * Reduced scope of MCTL reset to just stop channel coms. * Added dummy read data to write commands * Changed _ to - seperators in string names and filenames * Dropped ------------ in header comment * Catchall'ed _update_ints() in _write handler. * Minor whitespace changes. * Use ZYNQ_XADC_FIFO_DEPTH instead of ARRAY_SIZE() ] Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Tested-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 11月, 2015 4 次提交
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由 Andrew Jones 提交于
Signed-off-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Message-id: 1446909925-12201-1-git-send-email-drjones@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Firstly, enable monitor mode and PSCI, both of which are features of this board. In addition to PSCI, this board also uses SMC for cache maintenance ops. This means we need a secure monitor to catch these and nop them. Use the ARM boot board-setup feature to implement this. The SMC trap implements the needed nop while all other traps will pen the CPU. As a KVM CPU cannot run in secure mode, do not do the board-setup if not running TCG. Report a warning explaining the limitation in this case. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 0fd0d12f0fa666c86616c89447861a70dbe27312.1447007690.git.crosthwaite.peter@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This board should not support CPU model override. This allows for easier patching of the board with being able to rely on the CPU type being correct. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 471a61e049c7ca6e82f5ef6668889a1d518c7e00.1447007690.git.crosthwaite.peter@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a flag that when set, will cause the primary CPU to start in secure mode, even if the overall boot is non-secure. This is useful for when there is a board-setup blob that needs to run from secure mode, but device and secondary CPU init should still be done as-normal for a non- secure boot. Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: d1170774d5446d715fced7739edfc61a5be931f9.1447007690.git.crosthwaite.peter@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 11月, 2015 1 次提交
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由 Peter Crosthwaite 提交于
Add the Allwinner A10 AHCI controller module to the SoC. Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: NJohn Snow <jsnow@redhat.com> Message-id: 69d6962f2d14a218bd07e9ac4ccd1947737cc30f.1445917756.git.crosthwaite.peter@gmail.com Signed-off-by: NJohn Snow <jsnow@redhat.com>
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- 04 11月, 2015 1 次提交
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由 Eduardo Habkost 提交于
This makes the purpose of the function clearer: it is not about the version of QEMU that's running, but the version string exposed in the emulated hardware. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: NJohn Snow <jsnow@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <1446233769-7892-3-git-send-email-ehabkost@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 03 11月, 2015 7 次提交
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由 Shannon Zhao 提交于
Use mp_affinity of ARMCPU as the CPU MPIDR instead of the CPU index. Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1446285001-7316-1-git-send-email-zhaoshenglong@huawei.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
When booting VM with GICv3, the kernel needs GICC ACPI subtable to initialize the CPUs, e.g. MPIDR information. This adds GICC ACPI subtable for GICv3, but set GICC base address only when gic_version == 2 since it donesn't need GICC base address for GICv3. Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1446131773-5018-1-git-send-email-shannon.zhao@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Graeme Gregory 提交于
According to ACPI specification 6.2.17 _CCA (Cache Coherency Attribute) this attribute is compulsory on ARM systems. Add this attribute to the PCI host bridges as required. Without this the kernel will produce the error [Firmware Bug]: PCI device 0000:00:00.0 fail to setup DMA. Signed-off-by: NGraeme Gregory <graeme.gregory@linaro.org> Message-id: 1446460786-13663-1-git-send-email-graeme.gregory@linaro.org Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Michael Davidsaver 提交于
Add GPIO in for the stellaris board which calls qemu_system_reset_request() on reset request. Signed-off-by: NMichael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Michael Davidsaver 提交于
Change armv7m_init to return the DeviceState* for the NVIC. This allows access to all GPIO blocks, not just the IRQ inputs. Move qdev_get_gpio_in() calls out of armv7m_init() into board code for stellaris and stm32f205 boards. Signed-off-by: NMichael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a Linux-specific pre-boot routine that matches the device- specific bootloaders behaviour. This is needed for modern Linux that expects the ARM PLL in SLCR to be a more even value (not 26). Cc: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 9a9025ea65572586b50dca4e5819032e3c436d64.1446182614.git.crosthwaite.peter@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add an API for boards to inject their own preboot software (or firmware) sequence. The software then returns to the bootloader via the link register. This allows boards to do their own little bits of firmware setup without needed to replace the bootloader completely (which is the requirement for existing firmware support). The blob is loaded by a callback if and only if doing a linux boot (similar to the existing write_secondary support). Rewrite the comment for the primary boot blob. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 070295644c6ac84696d743913296e8cfefb48c15.1446182614.git.crosthwaite.peter@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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