1. 31 10月, 2011 5 次提交
    • D
      pseries: Use Book3S-HV TCE acceleration capabilities · 0f5cb298
      David Gibson 提交于
      The pseries machine of qemu implements the TCE mechanism used as a
      virtual IOMMU for the PAPR defined virtual IO devices.  Because the
      PAPR spec only defines a small DMA address space, the guest VIO
      drivers need to update TCE mappings very frequently - the virtual
      network device is particularly bad.  This means many slow exits to
      qemu to emulate the H_PUT_TCE hypercall.
      
      Sufficiently recent kernels allow this to be mitigated by implementing
      H_PUT_TCE in the host kernel.  To make use of this, however, qemu
      needs to initialize the necessary TCE tables, and map them into itself
      so that the VIO device implementations can retrieve the mappings when
      they access guest memory (which is treated as a virtual DMA
      operation).
      
      This patch adds the necessary calls to use the KVM TCE acceleration.
      If the kernel does not support acceleration, or there is some other
      error creating the accelerated TCE table, then it will still fall back
      to full userspace TCE implementation.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      0f5cb298
    • D
      pseries: Allow KVM Book3S-HV on PPC970 CPUS · 354ac20a
      David Gibson 提交于
      At present, using the hypervisor aware Book3S-HV KVM will only work
      with qemu on POWER7 CPUs.  PPC970 CPUs also have hypervisor
      capability, but they lack the VRMA feature which makes assigning guest
      memory easier.
      
      In order to allow KVM Book3S-HV on PPC970, we need to specially
      allocate the first chunk of guest memory (the "Real Mode Area" or
      RMA), so that it is physically contiguous.
      
      Sufficiently recent host kernels allow such contiguous RMAs to be
      allocated, with a kvm capability advertising whether the feature is
      available and/or necessary on this hardware.  This patch enables qemu
      to use this support, thus allowing kvm acceleration of pseries qemu
      machines on PPC970 hardware.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      
      ---
      
      agraf: fix to use memory api
      354ac20a
    • D
      pseries: Support SMT systems for KVM Book3S-HV · e97c3636
      David Gibson 提交于
      Alex Graf has already made qemu support KVM for the pseries machine
      when using the Book3S-PR KVM variant (which runs the guest in
      usermode, emulating supervisor operations).  This code allows gets us
      very close to also working with KVM Book3S-HV (using the hypervisor
      capabilities of recent POWER CPUs).
      
      This patch moves us another step towards Book3S-HV support by
      correctly handling SMT (multithreaded) POWER CPUs.  There are two
      parts to this:
      
       * Querying KVM to check SMT capability, and if present, adjusting the
         cpu numbers that qemu assigns to cause KVM to assign guest threads
         to cores in the right way (this isn't automatic, because the POWER
         HV support has a limitation that different threads on a single core
         cannot be in different guests at the same time).
      
       * Correctly informing the guest OS of the SMT thread to core mappings
         via the device tree.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      e97c3636
    • L
      ppc/e500_pci: Fix an array overflow issue · eeae2e7b
      Liu Yu-B13201 提交于
      When access PPCE500_PCI_IW1 the previous index get overflow.
      The patch fix the issue and update all to keep consistent style.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      eeae2e7b
    • L
      ppc/e500_pci: Fix code style · 6875dc8e
      Liu Yu-B13201 提交于
      Put trailing statements on next line.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Reviewed-by: NAndreas Färber <andreas.faerber@web.de>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6875dc8e
  2. 30 10月, 2011 5 次提交
  3. 28 10月, 2011 1 次提交
    • B
      Merge branch 'rth/vis2' of git://repo.or.cz/qemu/rth · b5a12aa2
      Blue Swirl 提交于
      * 'rth/vis2' of git://repo.or.cz/qemu/rth:
        target-sparc: Implement FALIGNDATA inline.
        target-sparc: Implement BMASK/BSHUFFLE.
        target-sparc: Implement ALIGNADDR* inline.
        target-sparc: Implement EDGE* instructions.
        target-sparc: Implement fpack{16,32,fix}.
        target-sparc: Implement PDIST.
        target-sparc: Do exceptions management fully inside the helpers.
        target-sparc: Change fpr representation to doubles.
        target-sparc: Undo cpu_fpr rename.
        target-sparc: Extract float128 move to a function.
        target-sparc: Extract common code for floating-point operations.
        target-sparc: Make FPU/VIS helpers const when possible.
        target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
        target-sparc: Add accessors for double-precision fpr access.
        target-sparc: Mark fprs dirty in store accessor.
        target-sparc: Add accessors for single-precision fpr access.
      b5a12aa2
  4. 27 10月, 2011 26 次提交
  5. 26 10月, 2011 3 次提交