1. 23 6月, 2020 11 次提交
  2. 22 6月, 2020 1 次提交
    • P
      Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200619-3' into staging · 171199f5
      Peter Maydell 提交于
      This is a range of patches for RISC-V.
      
      Some key points are:
       - Generalise the CPU init functions
       - Support the SiFive revB machine
       - Improvements to the Hypervisor implementation and error checking
       - Connect some OpenTitan devices
       - Changes to the sifive_u machine to support U-boot
      
      v2:
       - Fix missing realise assert
      
      # gpg: Signature made Fri 19 Jun 2020 17:34:34 BST
      # gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
      # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
      # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054
      
      * remotes/alistair/tags/pull-riscv-to-apply-20200619-3: (32 commits)
        hw/riscv: sifive_u: Add a dummy DDR memory controller device
        hw/riscv: sifive_u: Sort the SoC memmap table entries
        hw/riscv: sifive_u: Support different boot source per MSEL pin state
        hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
        target/riscv: Rename IBEX CPU init routine
        hw/riscv: sifive_u: Add a new property msel for MSEL pin state
        hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
        hw/riscv: sifive_u: Add reset functionality
        hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
        hw/riscv: sifive_u: Hook a GPIO controller
        hw/riscv: sifive_gpio: Add a new 'ngpio' property
        hw/riscv: sifive_gpio: Clean up the codes
        hw/riscv: sifive_u: Generate device tree node for OTP
        hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
        hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
        hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
        target/riscv: Use a smaller guess size for no-MMU PMP
        riscv/opentitan: Connect the UART device
        riscv/opentitan: Connect the PLIC device
        hw/intc: Initial commit of lowRISC Ibex PLIC
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      171199f5
  3. 21 6月, 2020 8 次提交
  4. 20 6月, 2020 2 次提交
    • P
      Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request' into staging · bae31bfa
      Peter Maydell 提交于
      audio: bugfixes for jack backend and gus emulation.
      
      # gpg: Signature made Fri 19 Jun 2020 14:17:22 BST
      # gpg:                using RSA key 4CB6D8EED3E87138
      # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
      # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
      # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
      # Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138
      
      * remotes/kraxel/tags/audio-20200619-pull-request:
        hw/audio/gus: Fix registers 32-bit access
        audio/jack: simplify the re-init code path
        audio/jack: honour the enable state of the audio device
        audio/jack: do not remove ports when finishing
        audio/jack: remove invalid set of input support bool
        audio/jack: remove unused stopped state
        audio/jack: fix invalid minimum buffer size check
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      bae31bfa
    • R
      qht: Fix threshold rate calculation · 06c4cc36
      Richard Henderson 提交于
      tests/qht-bench.c:287:29: error: implicit conversion from 'unsigned long'
        to 'double' changes value from 18446744073709551615
        to 18446744073709551616 [-Werror,-Wimplicit-int-float-conversion]
              *threshold = rate * UINT64_MAX;
                                ~ ^~~~~~~~~~
      
      Fix this by splitting the 64-bit constant into two halves,
      each of which is individually perfectly representable, the
      sum of which produces the correct arithmetic result.
      
      This is very likely just a sticking plaster over some underlying
      incorrect code, but it will suppress the warning for the moment.
      
      Cc: Emilio G. Cota <cota@braap.org>
      Reported-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
      Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      06c4cc36
  5. 19 6月, 2020 18 次提交