- 26 2月, 2016 32 次提交
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由 Andrew Baumann 提交于
This quirk is a workaround for the following hardware behaviour, on which UEFI (specifically, the bootloader for Windows on Pi2) depends: 1. at boot with an SD card present, the interrupt status/enable registers are initially zero 2. upon enabling it in the interrupt enable register, the card insert bit in the interrupt status register is immediately set 3. after a subsequent controller reset, the card insert interrupt does not fire, even if enabled in the interrupt enable register Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456436130-7048-3-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Baumann 提交于
This reverts commit 72369755. This change was poorly tested on my part. It squelched card insertion interrupts on reset, but that was not necessary because sdhci_reset() clears all the registers (via the call to memset), so the subsequent sdhci_insert_eject_cb() call never sees the card insert interrupt enabled. However, not calling the insert_eject_cb results in prnsts remaining 0, when it actually needs to be updated to indicate card presence and R/O status. Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456436130-7048-2-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Huth 提交于
Some header files in the include/hw/arm/ directory can be assigned to entries in the MAINTAINERS file. Signed-off-by: NThomas Huth <thuth@redhat.com> Message-id: 1456399324-24259-1-git-send-email-thuth@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Baumann 提交于
Recent changes to sdhci broke SD on raspi. This change mirrors the logic to create the SD card device at the board level. Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456351128-5560-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Wei Huang 提交于
pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which share the same read/write functions (pl061_read and pl061_write). However PL061 and Stellaris have different GPIO register definitions and pl061_read()/pl061_write() doesn't check it. This patch enforces checking on offset, preventing R/W into the reserved memory area. Signed-off-by: NWei Huang <wei@redhat.com> Message-id: 1455814580-17699-1-git-send-email-wei@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement the performance monitor register traps controlled by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance registers already have an access function to deal with the user-enable bit, and the TPM checks can be added there. We also need a new access function which only implements the TPM checks for use by the few not-EL0-accessible registers and by PMUSERENR_EL0 (which is always EL0-readable). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-3-git-send-email-peter.maydell@linaro.org Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Acked-by: NAlistair Francis <alistair.francis@xilinx.com>
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由 Peter Maydell 提交于
Fix two issues with our implementation of the SDCR: * it is only present from ARMv8 onwards * it does not contain several of the trap bits present in its 64-bit counterpart the MDCR_EL3 Put the register description in the right place so that it does not get enabled for ARMv7 and earlier, and give it a write function so that we can mask out the bits which should not be allowed to have an effect if EL3 is 32-bit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-2-git-send-email-peter.maydell@linaro.org Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Acked-by: NAlistair Francis <alistair.francis@xilinx.com>
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由 Peter Maydell 提交于
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Mode switches from Hyp to any other mode via the CPS and MRS instructions are illegal mode switches (though obviously switching via exception return is valid). Add this check to bad_mode_switch(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-11-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are given architected behaviour: * the mode field is unchanged * PSTATE.IL is set (so any subsequent instructions will UNDEF) * any other CPSR fields are written to as normal This is pretty much the same behaviour we picked for our UNPREDICTABLE handling, with the exception that for v8 we need to set the IL bit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-10-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In v8 trying to switch mode to Mon from Secure EL1 is an illegal mode switch. (In v7 this is impossible as all secure modes except User are at EL3.) We can handle this case by making a switch to Mon valid only if the current EL is 3, which then gives the correct answer whether EL3 is AArch32 or AArch64. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-9-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
We don't actually support Hyp mode yet, but add the correct checks for it to the bad_mode_switch() function for completeness. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-8-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The only case where we can attempt a cpsr_write() mode switch from User is from the gdbstub; all other cases are handled in the calling code (notably translate.c). Architecturally attempts to alter the mode bits from user mode are simply ignored (and not treated as a bad mode switch, which in v8 sets CPSR.IL). Make mode switches from User ignored in cpsr_write() as well, for consistency. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
When linux-user code is calling cpsr_write(), use a restrictive mask to ensure we are limiting the set of CPSR bits we update. In particular, don't allow the mode bits to be changed. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
MIPS patches 2016-02-26 Changes: * support for FPU and MSA in KVM guest * support for R6 Virtual Processors # gpg: Signature made Fri 26 Feb 2016 11:07:37 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160226: target-mips: implement R6 multi-threading mips/kvm: Support MSA in MIPS KVM guests mips/kvm: Support FPU in MIPS KVM guests mips/kvm: Support signed 64-bit KVM registers mips/kvm: Support unsigned KVM registers mips/kvm: Implement Config CP0 registers mips/kvm: Implement PRid CP0 register mips/kvm: Remove a couple of noisy DPRINTFs Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Update OpenBIOS images # gpg: Signature made Fri 26 Feb 2016 10:45:04 GMT using RSA key ID AE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" * remotes/mcayland/tags/qemu-openbios-signed: Update OpenBIOS images Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Mark Cave-Ayland 提交于
Update OpenBIOS images to SVN r1391 built from submodule. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Yongbok Kim 提交于
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Support the new KVM_CAP_MIPS_MSA capability, which allows MIPS SIMD Architecture (MSA) to be exposed to the KVM guest. The capability is enabled if the guest core has MSA according to its Config3 register. Various config bits are now writeable so that KVM is aware of the configuration (Config3.MSAP) and so that QEMU can save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR registers and the MSA vector registers are now saved/restored. Since the FP registers are a subset of the vector registers, they are omitted if the guest has MSA. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Support the new KVM_CAP_MIPS_FPU capability, which allows the host's FPU to be exposed to the KVM guest. The capability is enabled if the guest core has an FPU according to its Config1 register. Various config bits are now writeable so that KVM is aware of the configuration (Config1.FP) and so that QEMU can save/restore the guest modifiable bits (Config5.FRE, Config5.UFR, Config5.UFE). The FCSR/FIR registers and the floating point registers are now saved/restored (depending on the FR mode bit). Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64() since they take an int64_t pointer, and add separate signed 64-bit accessors. These will be used for double precision floating point registers. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Add KVM register access functions for the uint32_t type. This is required for FP and MSA control registers, which are represented as unsigned 32-bit integers. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Implement saving and restoring to KVM state of the Config CP0 registers (namely Config, Config1, Config2, Config3, Config4, and Config5). These control the features available to a guest, and a few of the fields will soon be writeable by a guest so QEMU needs to know about them so as not to clobber them on migration/savevm. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
Implement saving and restoring to KVM state of the Processor ID (PRid) CP0 register. This allows QEMU to control the PRid exposed to the guest instead of using the default set by KVM. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 James Hogan 提交于
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run() are particularly noisy during normal execution, and also not particularly helpful. Remove them so that more important debug messages can be more easily seen. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Peter Maydell 提交于
qemu-ga patch queue for 2.6 * fix w32 build breakage when VSS enabled * fix up wchar handling in guest-set-user-password * fix re-install handling for w32 MSI installer * add w32 support for guest-get-vcpus * add support for enums in guest-file-seek SEEK params instead of relying on platform-specific integer values # gpg: Signature made Thu 25 Feb 2016 16:59:13 GMT using RSA key ID F108B584 # gpg: Good signature from "Michael Roth <flukshun@gmail.com>" # gpg: aka "Michael Roth <mdroth@utexas.edu>" # gpg: aka "Michael Roth <mdroth@linux.vnet.ibm.com>" * remotes/mdroth/tags/qga-pull-2016-02-25-tag: qga: fix w32 breakage due to missing osdep.h includes qga: check utf8-to-utf16 conversion qga: fix off-by-one length check qga: use wide-chars constants for wchar_t comparisons qga: use size_t for wcslen() return value qga: use more idiomatic qemu-style eol operators qga: implement the guest-get-vcpus for windows qemu-ga: Fixed minor version switch issue qga: Support enum names in guest-file-seek Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Michael Roth 提交于
requester.h relied on qemu/compiler.h definitions to handle GCC_FMT_ATTR() stub, but this include was removed as part of scripted clean-ups via 30456d5b: all: Clean up includes under the assumption that all C files would have included it via qemu/osdep.h at that point. requester.cpp was likely missed due to C++ files requiring manual/special handling as well as VSS build options needing to be enabled to trigger build failures. Fix this by including qemu/osdep.h. That in turn pulls in a macro from qapi/error.h that conflicts with a struct field name in requester.h, so fix that as well by renaming the field. While we're at it, fix up provider.cpp/install.cpp to include osdep.h as well. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Lluís Vilanova 提交于
This fixes double-definitions in bsd-user builds when using the UST tracing backend (which indirectly includes the system's "syscall.h"). Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 25 2月, 2016 8 次提交
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由 Marc-André Lureau 提交于
UTF8 to UTF16 conversion can fail for genuine reasons, let's check errors. Reported-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Marc-André Lureau 提交于
Laszlo Ersek said: "The length check is off by one (in the safe direction); it should be (nchars >= 2). The processing should be active for the wide string L"\r\n" -- resulting in the empty wide string --, I believe." Reported-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Marc-André Lureau 提交于
Reported-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Marc-André Lureau 提交于
Reported-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Marc-André Lureau 提交于
Reported-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Gal Hammer 提交于
Signed-off-by: NGal Hammer <ghammer@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> * report rather than assert when VCPU count == 0 * fix up subject: s/set-vcpus/get-vcpus/ Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Leonid Bloch 提交于
With automatically generated GUID, on minor version changes, an error occurred, stating that there is a problem with the installer. Now, a notification is shown, warning the user that another version of this product is already installed, and that configuration or removal of the existing version is possible through Add/Remove Programs on the Control Panel (expected behavior). Signed-off-by: NLeonid Bloch <leonid@daynix.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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由 Eric Blake 提交于
Magic constants are a pain to use, especially when we run the risk that our choice of '1' for QGA_SEEK_CUR might differ from the host or guest's choice of SEEK_CUR. Better is to use an enum value, via a qapi alternate type for back-compatibility. With this, {"command":"guest-file-seek", "arguments":{"handle":1, "offset":0, "whence":"cur"}} becomes a synonym for the older {"command":"guest-file-seek", "arguments":{"handle":1, "offset":0, "whence":1}} Signed-off-by: NEric Blake <eblake@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
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