- 22 2月, 2017 40 次提交
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由 Alex Zuepke 提交于
The Book-E TLB matching process should bail out early when a TLB entry matches, but the access permissions are wrong. The CPU will then raise a DSI error instead of a Data TLB error, as described for TLB matching in Freescale and IBM documents. Signed-off-by: NAlex Zuepke <azu@sysgo.de> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Sam Bobroff 提交于
The spapr-vlan device in QEMU has always presented it's MAC address in the device tree as an 8 byte value, even though PAPR requires it to be 6 bytes. This is because, at the time, AIX required the value to be 8 bytes. However, modern versions of AIX support the (correct) 6 byte value so they no longer require the workaround. It would be neatest to always provide a 6 byte value but that would cause a problem with old Linux kernel ibmveth drivers, so the old 8 byte value is still presented when necessary. Since commit 13f85203e (3.10, May 2013) the driver has been able to handle 6 or 8 byte addresses so versions after that don't need to be considered specially. Drivers from kernels before that can also handle either type of address, but not always: * If the first byte's lowest bits are 10, the address must be 6 bytes. * Otherwise, the address must be 8 bytes. (The two bits in question are significant in a MAC address: they indicate a locally-administered unicast address.) So to maintain compatibility the old 8 byte value is presented when the lowest two bits of the first byte are not 10. Signed-off-by: NSam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
Generic helper machine_query_hotpluggable_cpus() replaced target specific query_hotpluggable_cpus() callbacks so there is no need in it anymore. However inon NULL callback value is used to detect/report hotpluggable cpus support, therefore it can be removed completely. Replace it with MachineClass.has_hotpluggable_cpus boolean which is sufficient for the task. Suggested-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
All callbacks FOO_query_hotpluggable_cpus() are practically the same except of setting vcpus_count to different values. Convert them to a generic machine_query_hotpluggable_cpus() callback by moving vcpus_count initialization to per machine specific callback possible_cpu_arch_ids(). Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
Replace SPAPR specific cores[] array with generic machine->possible_cpus and store core objects there. It makes cores bookkeeping similar to x86 cpus and will allow to unify similar code. It would allow to replace cpu_index based NUMA node mapping with iproperty based one (for -device created cores) since possible_cpus carries board defined topology/layout. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
so it could be reused for SPAPR cores as well Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
Fill in CpuInstanceProperties once at board init time and just copy them whenever query_hotpluggable_cpus() is called. It will keep topology info always available without need to recalculate it every time it's needed. Considering it has NUMA node id, it will be used to keep NUMA node to cpu mapping instead of numa_info[i].node_cpu bitmasks. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
possible_cpus could be initialized earlier then cpu objects, i.e. when -smp is parsed so move init code to possible_cpu_arch_ids() interface func and do initialization on the first call. it should help later with making -numa cpu/-smp parsing a machine state properties. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
so that it would be possible to reuse it with spapr/virt-aarch64 targets. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Thomas Huth 提交于
hw_error() is for CPU related errors only (it prints out a register dump and calls abort()), so we should not use it if we just failed to load the bios image. Apart from that, realize() functions should not exit directly but always set the errp with error_setg() in case of errors instead. Additionally, move some code around and delete the bios memory subregion again in case of such an error, so that we leave a clean state when returning to the caller. Signed-off-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled whether ISI and DSI interrupts were directed to the hypervisor or the partition. These interrupts now go to the hypervisor irrespective, thus it is no longer necessary to check the vmp0 bit in the LPCR. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to Unsigned Doubleword format xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to Unsigned Word format Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to Double-Precision format using round to Odd xssqrtqpo: VSX Scalar Square Root Quad-Precision using round to Odd xssubqpo: VSX Scalar Subtract Quad-Precision using round to Odd In addition, fix the invalid bitmask in the instruction encoding of xssqrtqp[o]. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> CC: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction of PowerPC ISA 3.0. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
Implement float128_to_uint64() and use that to implement float128_to_uint64_round_to_zero() This is required by xscvqpudz instruction of PowerPC ISA 3.0. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Sam Bobroff 提交于
Programs run under qemu-ppc64 on an x86_64 host currently segfault if they use pthread_create() due to the adjustment made to the NIP in commit bd6fefe7. This patch changes cpu_loop() to set the NIP back to the pre-incremented value before calling do_syscall(), which causes the correct address to be used for the new thread and corrects the fault. Signed-off-by: NSam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Nikunj A Dadhania 提交于
Use the available wait instruction implementation. Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Nikunj A Dadhania 提交于
slbsync: SLB Synchoronize The instruction provides an ordering function for the effects of all slbieg instructions executed by the thread executing the slbsync instruction. Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Nikunj A Dadhania 提交于
slbieg: SLB Invalidate Entry Global Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Nikunj A Dadhania 提交于
Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Balamuruhan S 提交于
stwat: Store Word Atomic stdat: Store Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: NBalamuruhan S <bala24@linux.vnet.ibm.com> Signed-off-by: NHarish S <harisrir@linux.vnet.ibm.com> Signed-off-by: NAthira Rajeev <atrajeev@linux.vnet.ibm.com> [ implement stdat, use macro and combine both implementation ] Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Balamuruhan S 提交于
lwat: Load Word Atomic ldat: Load Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: NBalamuruhan S <bala24@linux.vnet.ibm.com> Signed-off-by: NHarish S <harisrir@linux.vnet.ibm.com> Signed-off-by: NAthira Rajeev <atrajeev@linux.vnet.ibm.com> [ combine both lwat/ldat implementation using macro ] Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Sam Bobroff 提交于
The last byte of the option vector was missing due to an off-by-one error. Without this fix, client architecture support negotiation will fail because the last byte of option vector 5, which contains the MMU support, will be missed. Signed-off-by: NSam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision xsminjdp: VSX Scalar Minimum Type-J Double-Precision Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision xsmincdp: VSX Scalar Minimum Type-C Double-Precision Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Thomas Huth 提交于
error_report() already puts a prefix with the program name in front of the error strings, so the "qemu:" prefix is not necessary here anymore. Reported-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Jose Ricardo Ziviani 提交于
xssubqp: VSX Scalar Subtract Quad-Precision. Signed-off-by: NJose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Jose Ricardo Ziviani 提交于
xssqrtqp: VSX Scalar Square Root Quad-Precision. Signed-off-by: NJose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Jose Ricardo Ziviani 提交于
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision. Signed-off-by: NJose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Jose Ricardo Ziviani 提交于
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer [with Inexact]. Signed-off-by: NJose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
spapr_core_unplug() were essentially spapr_core_unplug_request() handler that requested CPU removal and registered callback which did actual cpu core removali but it was called from spapr_machine_device_unplug() which is intended for actual object removal. Commit (cf632463 spapr: Memory hot-unplug support) sort of fixed it introducing spapr_machine_device_unplug_request() and calling spapr_core_unplug() but it hasn't renamed callback and by mistake calls it from spapr_machine_device_unplug(). However spapr_machine_device_unplug() isn't ever called for cpu core since spapr_core_release() doesn't follow expected hotunplug call flow which is: 1: device_del() -> hotplug_handler_unplug_request() -> set destroy_cb() 2: destroy_cb() -> hotplug_handler_unplug() -> object_unparent // actual device removal Fix it by renaming spapr_core_unplug() to spapr_core_unplug_request() which is called from spapr_machine_device_unplug_request() and making spapr_core_release() call hotplug_handler_unplug() which will call spapr_machine_device_unplug() -> spapr_core_unplug() to remove cpu core. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reveiwed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Igor Mammedov 提交于
spapr_core_pre_plug/spapr_core_plug/spapr_core_unplug() are managing wiring CPU core into spapr machine state and not internal CPU core state. So move them from spapr_cpu_core.c to spapr.c where other similar (spapr_memory_[foo]plug()) callbacks are located, which also matches x86 target practice. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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