- 01 9月, 2014 4 次提交
-
-
由 Bastian Koppelmann 提交于
Add instructions of SRC opcode format. Add micro-op generator functions for add, conditional add/sub and shi/shai. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Bastian Koppelmann 提交于
Add masks and opcodes for decoding TriCore instructions. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-6-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Bastian Koppelmann 提交于
Add tcg and cpu model initialization. Add gen_intermediate_code function. Activate target in configure and add softmmu config. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-5-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Bastian Koppelmann 提交于
Add TriCore target stubs, and QOM cpu, and Maintainer Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-