Factor out the VFP access checking code so that we can use it in the
leaf functions of the decodetree decoder.

We call the function full_vfp_access_check() so we can keep
the more natural vfp_access_check() for a version which doesn't
have the 'ignore_vfp_enabled' flag -- that way almost all VFP
insns will be able to use vfp_access_check(s) and only the
special-register access function will have to use
full_vfp_access_check(s, ignore_vfp_enabled).
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>

Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 VFP encodings.  At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.

We need to have one decoder for the unconditional insns and one for
the conditional insns, as otherwise the patterns for conditional
insns would incorrectly match against the unconditional ones too.

Since translate.c is over 14,000 lines long and we're going to be
touching pretty much every line of the VFP code as part of the
decodetree conversion, we create a new translate-vfp.inc.c to hold
the code which deals with VFP in the new scheme.  It should be
possible to convert this into a standalone translation unit
eventually, but the conversion process will be much simpler if we
simply #include it midway through translate.c to start with.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>

Typo comparing the sign of the field, twice, instead of also comparing
the mask of the field (which itself encodes both position and length).
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190604154225.26992-1-richard.henderson@linaro.org
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The ARM pseudocode installs the error_code into the original
pointer, not the encrypted pointer.  The difference applies
within the 7 bits of pac data; the result should be the sign
extension of bit 55.

Add a testcase to that effect.
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

In commit 80376c3f in 2010 we added a workaround for
some qbus buses not being connected to qdev devices -- if the
bus has no parent object then we register a reset function which
resets the bus on system reset (and unregister it when the
bus is unparented).

Nearly a decade later, we have now no buses in the tree which
are created with non-NULL parents, so we can remove the
workaround and instead just assert that if the bus has a NULL
parent then it is the main system bus.

(The absence of other parentless buses was confirmed by
code inspection of all the callsites of qbus_create() and
qbus_create_inplace() and cross-checked by 'make check'.)
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NDamien Hedde <damien.hedde@greensocs.com>
Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190523150543.22676-1-peter.maydell@linaro.org

The SMMUv3 ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NEric Auger <eric.auger@redhat.com>
Message-id: 20190524124829.2589-1-peter.maydell@linaro.org

The NSACR register allows secure code to configure the FPU
to be inaccessible to non-secure code. If the NSACR.CP10
bit is set then:
 * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2)
 * CPACR.{CP10,CP11} behave as if RAZ/WI
 * HCPTR.{TCP11,TCP10} behave as if RAO/WI

Note that we do not implement the NSACR.NSASEDIS bit which
gates only access to Advanced SIMD, in the same way that
we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE.
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 20190510110357.18825-1-peter.maydell@linaro.org

This replaces 3 target-specific implementations for BIT, BIF, and BSL.
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 20190518191934.21887-3-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

edid: add xmax + ymax properties, enable by default.

# gpg: Signature made Thu 13 Jun 2019 08:38:18 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/vga-20190613-pull-request:
  edid: flip the default to enabled
  edid: add xmax + ymax properties
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Fix vector arithmetic right shift helpers.

# gpg: Signature made Thu 13 Jun 2019 05:10:11 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190612:
  tcg: Fix typos in helper_gvec_sar{8,32,64}v
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

QAPI patches for 2019-06-12

# gpg: Signature made Wed 12 Jun 2019 17:44:50 BST
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-qapi-2019-06-12:
  qapi: Simplify how QAPIDoc implements its state machine
  file-posix: Add dynamic-auto-read-only QAPI feature
  qapi: Allow documentation for features
  qapi: Disentangle QAPIDoc code
  tests/qapi-schema: Error case tests for features in structs
  tests/qapi-schema: Test for good feature lists in structs
  qapi: Add feature flags to struct types
  block/gluster: update .help of BLOCK_OPT_PREALLOC option
  block/file-posix: update .help of BLOCK_OPT_PREALLOC option
  qapi/block-core: update documentation of preallocation parameter
  qdev: Delete unused LostTickPolicy "merge"
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

In fullscreen mode, the window property of cocoaView may not be the key
window, and the current implementation would not re-grab cursor by left click
in fullscreen mode after ungrabbed in fullscreen mode with hot-key ctrl-opt-g.

This patch used value of isFullscreen as a short-cirtuit condition for
relative input device grabbing.
Signed-off-by: NChen Zhang <tgfbeta@me.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 2D2F1191-E82F-4B54-A6E7-73FFB953DE93@me.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

On Mojave, absolute input device, i.e. tablet, had trouble re-grabbing
the cursor in re-entry into the virtual screen area. In some cases,
the `window` property of NSEvent object was nil after cursor exiting from
window, hinting that the `-locationInWindow` method would return value in
screen coordinates. The current implementation used raw locations from
NSEvent without considering whether the value was for the window coordinates
or the macOS screen coordinates, nor the zooming factor for Zoom-to-Fit in
fullscreen mode.

In fullscreen mode, the fullscreen cocoa window might not be the key
window, therefore the location of event in virtual coordinates should
suffice.

This patches fixed boundary check methods for cursor in normal
and fullscreen with/without Zoom-to-Fit in Mojave.

Note: CGRect, -convertRectToScreen: and -convertRectFromScreen: were
used in coordinates conversion for compatibility reason.
Signed-off-by: NChen Zhang <tgfbeta@me.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: FA3FBC4F-5379-4118-B997-58FE05CC58F9@me.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3' into staging

Various fixes and updates:

  - editor config tweak for shell scripts
  - iotest updates (still not default for make check)
  - various docker updates
  - gcc/ubsan updates for travis
  - some clean-ups for tests/vm (no serial autoinstall)
  - semihosting fix for Coverity
  - fixes for cputlb in 64-on-32 cases
  - gdbstub re-factor + maintainership update

# gpg: Signature made Wed 12 Jun 2019 17:55:04 BST
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3: (40 commits)
  gdbstub: Implement qemu physical memory mode
  gdbstub: Clear unused variables in gdb_handle_packet
  gdbstub: Implement target halted (? pkt) with new infra
  gdbstub: Implement generic set/query (Q/q pkt) with new infra
  gdbstub: Implement v commands with new infra
  gdbstub: Implement step (s pkt) with new infra
  gdbstub: Implement file io (F pkt) with new infra
  gdbstub: Implement read all registers (g pkt) with new infra
  gdbstub: Implement write all registers (G pkt) with new infra
  gdbstub: Implement read memory (m pkt) with new infra
  gdbstub: Implement write memory (M pkt) with new infra
  gdbstub: Implement get register (p pkt) with new infra
  gdbstub: Implement set register (P pkt) with new infra
  gdbstub: Implement breakpoint commands (Z/z pkt) with new infra
  gdbstub: Implement set_thread (H pkt) with new infra
  gdbstub: Implement continue with signal (C pkt) with new infra
  gdbstub: Implement continue (c pkt) with new infra
  gdbstub: Implement thread_alive (T pkt) with new infra
  gdbstub: Implement deatch (D pkt) with new infra
  gdbstub: Add infrastructure to parse cmd packets
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Reviewed-by: NMichael S. Tsirkin <mst@redhat.com>
Message-id: 20190607083444.32175-1-kraxel@redhat.com

Add new properties to allow setting the maximum display resolution.
Resolutions larger than that will not be included in the mode list.
In linux guests xrandr can be used to list modes.

Note: The existing xres and yres properties set the preferred display
resolution, i.e. the mode should be first in the mode list and guests
should use it by default.
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Message-id: 20190607083429.31943-1-kraxel@redhat.com

The loop is written with scalars, not vectors.
Use the correct type when incrementing.

Fixes: 5ee5c14cReported-by: NLaurent Vivier <lvivier@redhat.com>
Tested-by: NLaurent Vivier <lvivier@redhat.com>
Reviewed-by: NLaurent Vivier <lvivier@redhat.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

Add a new query/set which changes the memory GDB sees to physical memory
only.

gdb> maint packet qqemu.PhyMemMode
will reply the current phy_mem_mode state (1 for enabled, 0 for disabled)
gdb> maint packet Qqemu.PhyMemMode:1
Will make GDB read/write only to physical memory, set to 0 to disable
Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-21-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-20-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Note: The user-mode thread-id has been correctly reported since bd88c780Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-19-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

The generic set/query packets contains implementation for varioius
sub-commands which are required for GDB and also additional commands
which are QEMU specific.

To see which QEMU specific commands are available use the command
gdb> maintenance packet qqemu.Supported

Currently the only implemented QEMU specific command is the command
that sets the single step behavior.

gdb> maintenance packet qqemu.sstepbits
Will display the MASK bits used to control the single stepping.

gdb> maintenance packet qqemu.sstep
Will display the current value of the mask used when single stepping.

gdb> maintenance packet Qqemu.sstep:HEX_VALUE
Will change the single step mask.
Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-18-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-17-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-16-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-15-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-14-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-13-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-12-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-11-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-10-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-9-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-8-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-7-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-6-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-5-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-4-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Message-Id: <20190529064148.19856-3-arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

Signed-off-by: NJon Doron <arilou@gmail.com>
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-2-arilou@gmail.com>
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>

While size_t is defined to happily access the biggest host object this
isn't the case when generating masks for 64 bit guests on 32 bit
hosts. Otherwise we end up truncating the address when we fall back to
our unaligned helper.

Fixes: https://bugs.launchpad.net/qemu/+bug/1831545Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Tested-by: NAndrew Randrianasulu <randrianasulu@gmail.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>

As I've been reviewing a lot of this recently and I'm going to put
together a pull request I'd better keep an eye on it. Philippe has
also volunteered to be a reviewer.
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>

Instead of doing the full real to 64 bit dance we are attempting to
leverage Xen's PVH boot spec to go from 32 bit to 64 bit.
Signed-off-by: NAlex Bennée <alex.bennee@linaro.org>