- 27 4月, 2013 9 次提交
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由 Richard Henderson 提交于
An armv7 extension implements division, present on Cortex A15. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
We have BFI and BFC available for implementing it. Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
This allows us to emit CMN instructions. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
This allows the generation of RSB instructions. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
This greatly improves code generation for addition of small negative constants. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that any helper with more than 4 arguments would clobber the saved regs. Realizing that we're supposed to have this memory pre-allocated means we can clean up the tcg_out_arg functions, which were trying to do more stack allocation. Allocate stack memory for the TCG temporaries while we're at it. Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 24 2月, 2013 1 次提交
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由 Richard Henderson 提交于
We even had the encoding of smull already handy... Cc: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 19 1月, 2013 1 次提交
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由 Peter Maydell 提交于
Silence a (legitimate) complaint about missing parentheses: tcg/arm/tcg-target.c: In function ‘tcg_out_qemu_ld’: tcg/arm/tcg-target.c:1148:5: error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] tcg/arm/tcg-target.c: In function ‘tcg_out_qemu_st’: tcg/arm/tcg-target.c:1357:5: error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] which meant that we would mistakenly always assert if running a QEMU built with debug enabled on ARM. Signed-off-by: NPeter Maydell <peter.maydelL@linaro.org> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 19 12月, 2012 1 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 24 11月, 2012 2 次提交
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由 Aurelien Jarno 提交于
The bswap16 TCG opcode assumes that the high bytes of the temp equal to 0 before calling it. The ARM backend implementation takes this assumption to slightly optimize the generated code. The same implementation is called for implementing the cross-endian qemu_st16 opcode, where this assumption is not true anymore. One way to fix that would be to zero the high bytes before calling it. Given the store instruction just ignore them, it is possible to provide a slightly more optimized version. With ARMv6+ the rev16 instruction does the work correctly. For lower ARM versions the patch provides a version which behaves correctly with non-zero high bytes, but fill them with junk. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
The TCG arm backend considers likely that the offset to the TLB entries does not exceed 12 bits for mem_index = 0. In practice this is not true for at least the MIPS target. The current patch fixes that by loading the bits 23-12 with a separate instruction, and using loads with address writeback, independently of the value of mem_idx. In total this allow a 24-bit offset, which is a lot more than needed. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 17 10月, 2012 2 次提交
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由 Peter Maydell 提交于
Implement movcond_i32 for ARM, as the sequence mov dst, v2 (implicitly done by the tcg common code) cmp c1, c2 movCC dst, v1 Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
The code to emit either an immediate cmp or a register cmp insn is duplicated in several places; factor it out into its own function. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 07 10月, 2012 2 次提交
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由 Richard Henderson 提交于
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: NRichard Henderson <rth@twiddle.net> Acked-by: NBlue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 05 10月, 2012 1 次提交
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由 Peter Maydell 提交于
Use the recently introduced tcg_out_mov_reg() function rather than the equivalent inline code. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NStefan Hajnoczi <stefanha@gmail.com>
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- 22 9月, 2012 1 次提交
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由 Stefan Weil 提交于
The TCG targets no longer need individual implementations. Since commit 6a18ae2d, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 16 9月, 2012 1 次提交
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由 Blue Swirl 提交于
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 27 8月, 2012 1 次提交
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由 Peter Maydell 提交于
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers was broken in that it did not respect the ABI requirement that 64 bit values were passed in even-odd register pairs. The simplest way to fix this is to implement some new utility functions for marshalling function arguments into the correct registers and stack, so that the code which sets up the address and data arguments does not need to care whether there has been a preceding env argument. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 18 3月, 2012 1 次提交
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由 Blue Swirl 提交于
Optionally, make memory access helpers take a parameter for CPUState instead of relying on global env. On most targets, perform simple moves to reorder registers. On i386, switch from regparm(3) calling convention to standard stack-based version. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 15 3月, 2012 1 次提交
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由 Andreas Färber 提交于
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 13 1月, 2012 1 次提交
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由 Aurelien Jarno 提交于
ARM still doesn't support 16GB buffers in 32-bit modes, replace the 16GB by 16MB in the comment. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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- 15 12月, 2011 1 次提交
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由 Dr. David Alan Gilbert 提交于
On ARM, don't map the code buffer at a fixed location, and fix up the call/goto tcg routines to let it do long jumps. Mapping the code buffer at a fixed address could sometimes result in it being mapped over the top of the heap with pretty random results. Signed-off-by: NDr. David Alan Gilbert <david.gilbert@linaro.org> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>
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- 15 11月, 2011 1 次提交
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由 Richard Henderson 提交于
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi. Signed-off-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 01 10月, 2011 1 次提交
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由 Peter Maydell 提交于
Remove the unused function tcg_out_addi() from the ARM TCG backend; this fixes a compilation failure on ARM hosts with newer gcc. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 27 6月, 2011 2 次提交
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由 Blue Swirl 提交于
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 24 3月, 2011 1 次提交
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由 Peter Maydell 提交于
Although the TCG generated code is always in ARM mode, it is possible that the host code was compiled by gcc in Thumb mode (this is often the default for Linux distributions targeting ARM v7 only). Handle this by using BLX imm when doing a call from ARM into Thumb mode. Since BLX imm is not a conditionalisable instruction, we make tcg_out_call() no longer take a condition code; we were only ever using it with COND_AL anyway. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>
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- 12 1月, 2011 1 次提交
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由 Aurelien Jarno 提交于
Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 10 1月, 2011 1 次提交
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由 Aurelien Jarno 提交于
Improve constant loading in two ways: - On all ARM versions, it's possible to load 0xffffff00 = -0x100 using the mvn rd, #0. Fix the conditions. - On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant to load. This is very useful for example to load constants where the low byte is 0. This reduce the generated code size by about 7%. Also fix the coding style at the same time. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 08 1月, 2011 2 次提交
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由 Aurelien Jarno 提交于
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of a 64 bit word before saving it. This patch fixes that. Acked-by: NAndrzej Zaborowski <balrogg@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
QEMU uses code retranslation to restore the CPU state when an exception happens. For it to work the retranslation must not modify the generated code. This is what is currently implemented in ARM TCG. However on CPU that don't have icache/dcache/memory synchronised like ARM, this requirement is stronger and code retranslation must not modify the generated code "atomically", as the cache line might be flushed at any moment (interrupt, exception, task switching), even if not triggered by QEMU. The probability for this to happen is very low, and depends on cache size and associativiy, machine load, interrupts, so the symptoms are might happen randomly. This requirement is currently not followed in tcg/arm, for the load/store code, which basically has the following structure: 1) tlb access code is written 2) conditional fast path code is written 3) branch is written with a temporary target 4) slow path code is written 5) branch target is updated The cache lines corresponding to the retranslated code is not flushed after code retranslation as the generated code is supposed to be the same. However if the cache line corresponding to the branch instruction is flushed between step 3 and 5, and is not flushed again before the code is executed again, the branch target is wrong. In the guest, the symptoms are MMU page fault at a random addresses, which leads to kernel page fault or segmentation faults. The patch fixes this issue by avoiding writing the branch target until it is known, that is by writing only the branch instruction first, and later only the offset. This fixes booting linux guests on ARM hosts (tested: arm, i386, mips, mipsel, sh4, sparc). Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 09 6月, 2010 2 次提交
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由 Richard Henderson 提交于
Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Richard Henderson 提交于
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 25 4月, 2010 1 次提交
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由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 19 4月, 2010 2 次提交
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由 Aurelien Jarno 提交于
There is statistically almost 0 chances to use this code, so remove it. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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