1. 25 9月, 2015 1 次提交
  2. 18 9月, 2015 1 次提交
    • P
      target-mips: improve exception handling · 9c708c7f
      Pavel Dovgaluk 提交于
      This patch improves exception handling in MIPS.
      Instructions generate several types of exceptions.
      When exception is generated, it breaks the execution of the current
      translation block. Implementation of the exceptions handling does not
      correctly restore icount for the instruction which caused the exception.
      In most cases icount will be decreased by the value equal to the size of
      TB. This patch passes pointer to the translation block internals to the
      exception handler. It allows correct restoring of the icount value.
      Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
      Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
      Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
      [leon.alrae@imgtec.com: avoid retranslation in linux-user SC, break lines
       which are over 80 chars, remove v3 changelog from the commit message]
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      9c708c7f
  3. 11 9月, 2015 1 次提交
  4. 13 8月, 2015 1 次提交
  5. 09 7月, 2015 1 次提交
  6. 12 6月, 2015 3 次提交
    • L
      target-mips: add MTHC0 and MFHC0 instructions · 5204ea79
      Leon Alrae 提交于
      Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
      upper word of extended to 64-bits CP0 registers.
      
      In MIPS64, when CP0 destination register specified is the EntryLo0 or
      EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
      EntryLo1. This is to compensate for RI and XI, which were shifted to bits
      63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
      functions for EntryLo0 and EntryLo1.
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
      5204ea79
    • L
      target-mips: add CP0.PageGrain.ELPA support · e117f526
      Leon Alrae 提交于
      CP0.PageGrain.ELPA enables support for large physical addresses. This field
      is encoded as follows:
      0: Large physical address support is disabled.
      1: Large physical address support is enabled.
      
      If this bit is a 1, the following changes occur to coprocessor 0 registers:
      - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and
        concatenated with the PFN field to form the full page frame number.
      - Access to optional COP0 registers with PA extension, LLAddr, TagLo is
        defined.
      
      P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if
      XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode.
      In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0).
      
      env->PABITS value is constant and indicates maximum PABITS available on
      a core, whereas env->PAMask is calculated from env->PABITS and is also
      affected by CP0.PageGrain.ELPA.
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
      e117f526
    • L
      target-mips: extend selected CP0 registers to 64-bits in MIPS32 · 284b731a
      Leon Alrae 提交于
      Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
      
      Introduce gen_move_low32() function which moves low 32 bits from 64-bit
      temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
      MIPS32.
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
      284b731a
  7. 11 6月, 2015 2 次提交
  8. 11 3月, 2015 3 次提交
    • L
      target-mips: add missing MSACSR and restore fp_status and hflags · 64451111
      Leon Alrae 提交于
      Save MSACSR state. Also remove fp_status, msa_fp_status, hflags and restore
      them in post_load() from the architectural registers.
      Float exception flags are not present in vmstate. Information they carry
      is used only by softfloat caller who translates them into MIPS FCSR.Cause,
      FCSR.Flags and then they are cleared. Therefore there is no need for saving
      them in vmstate.
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      64451111
    • L
      target-mips: replace cpu_save/cpu_load with VMStateDescription · 04cd7962
      Leon Alrae 提交于
      Create VMStateDescription for MIPS CPU. The new structure contains exactly the
      same fields as before, therefore leaving existing version_id.
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      04cd7962
    • E
      cpu: Make cpu_init() return QOM CPUState object · 2994fd96
      Eduardo Habkost 提交于
      Instead of making cpu_init() return CPUArchState, return CPUState.
      
      Changes were made using the Coccinelle semantic patch below.
      
        @@
        typedef CPUState;
        identifier e;
        expression args;
        type CPUArchState;
        @@
        -   e =
        +   cpu =
                cpu_init(args);
        -   if (!e) {
        +   if (!cpu) {
                ...
            }
        -   cpu = ENV_GET_CPU(env);
        +   e = cpu->env_ptr;
      
        @@
        identifier new_env, new_cpu, env, cpu;
        type CPUArchState;
        expression args;
        @@
        -{
        -   CPUState *cpu = ENV_GET_CPU(env);
        -   CPUArchState *new_env = cpu_init(args);
        -   CPUState *new_cpu = ENV_GET_CPU(new_env);
        +{
        +   CPUState *cpu = ENV_GET_CPU(env);
        +   CPUState *new_cpu = cpu_init(args);
        +   CPUArchState *new_env = new_cpu->env_ptr;
            ...
        }
      
        @@
        identifier c, cpu_init_func, cpu_model;
        type StateType, CPUType;
        @@
        -static inline StateType* cpu_init(const char *cpu_model)
        -{
        -   CPUType *c = cpu_init_func(cpu_model);
        (
        -   if (c == NULL) {
        -       return NULL;
        -   }
        -   return &c->env;
        |
        -   if (c) {
        -       return &c->env;
        -   }
        -   return NULL;
        )
        -}
        +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model))
      
        @@
        identifier cpu_init_func;
        identifier model;
        @@
        -#define cpu_init(model) (&cpu_init_func(model)->env)
        +#define cpu_init(model) CPU(cpu_init_func(model))
      Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
      Cc: Blue Swirl <blauwirbel@gmail.com>
      Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Cc: Riku Voipio <riku.voipio@iki.fi>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Michael Walle <michael@walle.cc>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Leon Alrae <leon.alrae@imgtec.com>
      Cc: Anthony Green <green@moxielogic.com>
      Cc: Jia Liu <proljc@gmail.com>
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Max Filippov <jcmvbkbc@gmail.com>
      [AF: Fixed up cpu_copy() manually]
      Signed-off-by: NAndreas Färber <afaerber@suse.de>
      2994fd96
  9. 20 1月, 2015 1 次提交
    • P
      exec.c: Drop TARGET_HAS_ICE define and checks · ec53b45b
      Peter Maydell 提交于
      The TARGET_HAS_ICE #define is intended to indicate whether a target-*
      guest CPU implementation supports the breakpoint handling. However,
      all our guest CPUs have that support (the only two which do not
      define TARGET_HAS_ICE are unicore32 and openrisc, and in both those
      cases the bp support is present and the lack of the #define is just
      a bug). So remove the #define entirely: all new guest CPU support
      should include breakpoint handling as part of the basic implementation.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
      ec53b45b
  10. 16 12月, 2014 5 次提交
  11. 07 11月, 2014 1 次提交
  12. 03 11月, 2014 12 次提交
  13. 14 10月, 2014 1 次提交
    • Y
      target-mips: fix broken MIPS16 and microMIPS · b231c103
      Yongbok Kim 提交于
      Commit 240ce26a broke MIPS16 and microMIPS support as it didn't
      care those branches and jumps don't have delay slot in
      MIPS16 and microMIPS.
      
      This patch introduces a new argument delayslot_size to the
      gen_compute_branch() indicating size of delay slot {0, 2, 4}.
      And the information is used to call handle_delay_slot() forcingly
      when no delay slot is required.
      
      There are some microMIPS branch and jump instructions that requires
      exact size of instruction in the delay slot. For indicating
      these instructions, MIPS_HFLAG_BDS_STRICT flag is introduced.
      
      Those fictional branch opcodes defined to support MIPS16 and
      microMIPS are no longer needed.
      Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
      Tested-by: NJonas Gorski <jogo@openwrt.org>
      Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
      [leon.alrae@imgtec.com: cosmetic changes]
      Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
      b231c103
  14. 13 10月, 2014 1 次提交
  15. 19 6月, 2014 1 次提交
  16. 05 6月, 2014 1 次提交
  17. 27 3月, 2014 1 次提交
  18. 14 3月, 2014 3 次提交