- 08 1月, 2014 5 次提交
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由 Claudio Fontana 提交于
This patch adds support for C3.5.3 Add/subtract (with carry): instructions ADC, ADCS, SBC, SBCS. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The common pattern for system registers in a 64-bit capable ARM CPU is that when in AArch32 the cp15 register is a view of the bottom 32 bits of the 64-bit AArch64 system register; writes in AArch32 leave the top half unchanged. The most natural way to model this is to have the state field in the CPU struct be a 64 bit value, and simply have the AArch32 TCG code operate on a pointer to its lower half. For aarch64-linux-user the only registers we need to share like this are the thread-local-storage ones. Widen their fields to 64 bits and provide the 64 bit reginfo struct to make them visible in AArch64 state. Note that minor cleanup of the AArch64 system register encoding space means We can share the TPIDR_EL1 reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0. Since we're touching almost every line in QEMU that uses the c13_tls* fields in this patch anyway, we take the opportunity to rename them in line with the standard ARM architectural names for these registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0 Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The AArch64 equivalent of the traditional AArch32 cp15 coprocessor registers is the set of instructions MRS/MSR/SYS/SYSL, which cover between them both true system registers and the "operations with side effects" such as cache maintenance which in AArch32 are mixed in with other cp15 registers. Implement these instructions to look in the cpregs hashtable for the register or operation. Since we don't yet populate the cpregs hashtable with any registers with the "AA64" bit set, everything will still UNDEF at this point. MSR/MRS is the first user of is_jmp = DISAS_UPDATE, so fix an infelicity in its handling where the main loop was requiring the caller to do the update of PC rather than just doing it itself. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The cpregs APIs used by the decoder (get_arm_cp_reginfo() and cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*. This is problematic for the A64 decoder, which doesn't pass the environment pointer around everywhere the way the 32 bit decoder does. Adjust the parameters these functions take so that we can copy only the relevant info from the CPUARMState into the DisasContext and then use that. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 05 1月, 2014 2 次提交
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由 Peter Maydell 提交于
Update the generic cpreg support code to also handle AArch64: AArch64-visible registers coexist in the same hash table with AArch32-visible ones, with a bit in the hash key distinguishing them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
define_one_arm_cp_reg_with_opaque() has a set of nested loops which insert a cpreg entry into the hashtable for each of the possible opc/crn/crm values allowed by wildcard specifications. We're about to add an extra loop to this nesting, so pull the core of the loop (which adds a single entry to the hashtable) out into its own function for clarity. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 24 12月, 2013 10 次提交
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由 Peter Maydell 提交于
Implement FMOV, ie non-converting moves between general purpose registers and floating point registers. This is a subtype of the floating point <-> integer instruction class. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add a top level decoder skeleton for FP instructions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
Add decoding for the exception generating instructions, and implement SVC (syscalls) and BRK (software breakpoint). Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation for the "Data-processing (3 source)" family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alex Bennée 提交于
This patch adds emulation for the mov wide instructions (MOVN, MOVZ, MOVK). Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alex Bennée 提交于
Implement the non-carry forms of addition and subtraction (immediate, extended register and shifted register). This includes the code to calculate NZCV if the instruction calls for setting the flags. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alex Bennée 提交于
This adds support for the pre/post-index ld/st forms with immediate offsets as well as the un-scaled immediate form (which are all variations on the same 9-bit immediate instruction form). Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alex Bennée 提交于
This adds support for the load/store forms using a register offset. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alex Bennée 提交于
This adds support for the forms of ld/st with a 12 bit unsigned immediate offset. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
This patch support the basic load and store pair instructions and includes the generic helper functions: * do_gpr_st() * do_fp_st() * do_gpr_ld() * do_fp_ld() * read_cpu_reg_sp() * gen_check_sp_alignment() The last function gen_check_sp_alignment() is a NULL op currently but put in place to make it easy to add SP alignment checking later. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 23 12月, 2013 1 次提交
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由 Alexander Graf 提交于
The recent VSX patches broken compilation of QEMU when configurated with --enable-debug, as it was treating "target long" TCG variables as "i64" which is not true for 32bit targets. This patch fixes all the places that the compiler has found to use the correct variable type and if necessary manually cast. Reported-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 21 12月, 2013 4 次提交
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git://github.com/agraf/qemu由 Aurelien Jarno 提交于
Patch queue for s390 - 2013-12-18 This covers mostly minor bug fixes and implements the SIGP START hypercall which allows to start a remote CPU without changing its state. Cornelia Huck (1): s390x/kvm: Fix diagnose handling. Thomas Huth (7): s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Removed s390_store_status stub s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Implemented SIGP START s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/ioinst: CHSC has to set a condition code * tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu: s390x/ioinst: CHSC has to set a condition code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Implemented SIGP START s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Removed s390_store_status stub s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Fix diagnose handling.
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由 Aurelien Jarno 提交于
Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
The comments apply to 8-bit stores, not 8-byte stores. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 20 12月, 2013 18 次提交
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由 Anthony Liguori 提交于
Patch queue for ppc - 2013-12-20 Alexander Graf (3): PPC: Use default pci bus name for grackle and heathrow roms: Flush icache when writing roms to guest memory PPC: Add VSX to hflags Alexey Kardashevskiy (5): powerpc: add PVR mask support target-ppc: move POWER7+ to a separate family spapr-rtas: replace return code constants with macros spapr-rtas: add ibm, (get|set)-system-parameter spapr: make sure RMA is in first mode of first memory node Greg Kurz (1): target-ppc: add stubs for KVM breakpoints Paolo Bonzini (1): spapr: tie spapr-nvram to -pflash Paul Mackerras (1): spapr: limit numa memory regions by ram size Peter Crosthwaite (2): device_tree: s/qemu_devtree/qemu_fdt globally device_tree: qemu_fdt_setprop: Rename val_array arg Tom Musta (19): Declare and Enable VSX Add MSR VSX and Associated Exception Add VSX Instruction Decoders Add VSR to Global Registers Add lxvd2x Add stxvd2x Add xxpermdi Add lxsdx Add lxvdsx Add lxvw4x Add stxsdx Add stxvw4x Add VSX Scalar Move Instructions Add VSX Vector Move Instructions Add Power7 VSX Logical Instructions Add xxmrgh/xxmrgl Add xxsel Add xxspltw Add xxsldwi * agraf/tags/signed-ppc-for-upstream: (32 commits) spapr: limit numa memory regions by ram size spapr: make sure RMA is in first mode of first memory node device_tree: qemu_fdt_setprop: Rename val_array arg device_tree: s/qemu_devtree/qemu_fdt globally PPC: Add VSX to hflags Add xxsldwi Add xxspltw Add xxsel Add xxmrgh/xxmrgl Add Power7 VSX Logical Instructions Add VSX Vector Move Instructions Add VSX Scalar Move Instructions roms: Flush icache when writing roms to guest memory spapr: tie spapr-nvram to -pflash PPC: Use default pci bus name for grackle and heathrow spapr-rtas: add ibm, (get|set)-system-parameter spapr-rtas: replace return code constants with macros target-ppc: move POWER7+ to a separate family Add stxvw4x Add stxsdx ...
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由 Paul Mackerras 提交于
This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Peter Crosthwaite 提交于
Looking at the implementation, this doesn't really have a lot to do with arrays. Its just a pointer to a buffer and is passed through to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it consistent with libfdt, which in the wrapped function just calls it "val". Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Peter Crosthwaite 提交于
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We generate different code depending on whether MSR_VSX is set or clear, so it needs to be part of our hflags too which indicate whether we're still in the same translation block cache bucket. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Shift Left Double by Word Immediate (xxsldwi) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Select (xxsel) instruction. The xxsel instruction has four VSR operands. Thus the xC instruction decoder is added. The xxsel instruction is massively overloaded in the opcode table since only bits 26 and 27 are opcode bits. This overloading is done in matrix fashion with two macros (GEN_XXSEL_ROW and GEN_XX_SEL). V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation using tcg_gen_andc_i64. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Merge High Word and VSX Merge Low Word instructions. V2: Now implemented using deposit (per Richard Henderson's comment) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Paolo Bonzini 提交于
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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