提交 · 028e2a7b876631eff165cac59eb43bdb2dcc213b · openeuler / qemu

19 5月, 2018 5 次提交

target/arm: Implement SVE Predicate Misc Group · 028e2a7b

由 Richard Henderson 提交于 5月 18, 2018

Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-8-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

028e2a7b

target/arm: Implement SVE Predicate Logical Operations Group · 516e246a

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-7-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

516e246a

target/arm: Implement SVE predicate test · 9e18d7a6

由 Richard Henderson 提交于 5月 18, 2018

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-6-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

9e18d7a6

target/arm: Implement SVE load vector/predicate · d1822297

由 Richard Henderson 提交于 5月 18, 2018

Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-5-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

d1822297

target/arm: Add SVE decode skeleton · 38388f7e

由 Richard Henderson 提交于 5月 18, 2018

Including only 4, as-yet unimplemented, instruction patterns
so that the whole thing compiles.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-3-richard.henderson@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

38388f7e