1. 20 6月, 2015 9 次提交
  2. 19 6月, 2015 4 次提交
  3. 18 6月, 2015 19 次提交
  4. 17 6月, 2015 8 次提交
    • P
      Merge remote-tracking branch 'remotes/agraf/tags/signed-s390-for-upstream' into staging · f754c3c9
      Peter Maydell 提交于
      Patch queue for s390 - 2015-06-17
      
      This is a special one. Two awesome features in one pull request:
      
        - CCW support for TCG
        - Watchpoint support for TCG
      
      To celebrate this, we also switch the default machine model from s390-virtio
      to s390-ccw and give users a fully working s390x model again!
      
      # gpg: Signature made Wed Jun 17 11:42:26 2015 BST using RSA key ID 03FEDC60
      # gpg: Good signature from "Alexander Graf <agraf@suse.de>"
      # gpg:                 aka "Alexander Graf <alex@csgraf.de>"
      
      * remotes/agraf/tags/signed-s390-for-upstream: (26 commits)
        s390x: Switch to s390-ccw machine as default
        target-s390x: PER: add Breaking-Event-Address register
        target-s390x: PER instruction-fetch nullification event support
        target-s390x: PER store-using-real-address event support
        target-s390x: PER storage-alteration event support
        translate-all: fix watchpoints if retranslation not possible
        target-s390x: PER instruction-fetch event support
        target-s390x: PER successful-branching event support
        target-s390x: basic PER event handling
        target-s390x: add get_per_in_range function
        target-s390x: add get_per_atmid function
        target-s390x: add PER related constants
        target-s390x: mvc_fast_memmove: access memory through softmmu
        target-s390x: mvc_fast_memset: access memory through softmmu
        target-s390x: function to adjust the length wrt page boundary
        softmmu: provide tlb_vaddr_to_host function for user mode
        target-s390x: wire up I/O instructions in TCG mode
        target-s390x: wire up DIAG REIPL in TCG mode
        target-s390x: wire up DIAG IPL in TCG mode
        target-s390x: fix s390_cpu_initial_reset
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      f754c3c9
    • A
      s390x: Switch to s390-ccw machine as default · 1f68f1d3
      Alexander Graf 提交于
      We now finally have TCG support for the basic set of instructions necessary
      to run the s390-ccw machine. That means in any aspect possible that machine
      type is now superior to the legacy s390-virtio machine.
      
      Switch over to the ccw machine as default. That way people don't get a halfway
      broken machine with the s390x target.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
      Acked-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      1f68f1d3
    • A
      target-s390x: PER: add Breaking-Event-Address register · 3da0ab35
      Aurelien Jarno 提交于
      This patch adds support for PER Breaking-Event-Address register. Like
      real hardware, it save the current PSW address when the PSW address is
      changed by an instruction. We have to take care of optimizations QEMU
      does, a branch to the next instruction is still a branch.
      
      This register is copied to low core memory when a program exception
      happens.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      3da0ab35
    • A
      target-s390x: PER instruction-fetch nullification event support · 83bb1612
      Aurelien Jarno 提交于
      For the instruction-fetch nullification event, we just reuse the
      existing instruction-fetch code and trigger the exception immediately
      in that case.
      
      There is no need to save the CPU state in the TCG code as it has been
      saved by the previous instruction before calling the per_check_exception
      helper.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      83bb1612
    • A
      target-s390x: PER store-using-real-address event support · 2f543949
      Aurelien Jarno 提交于
      This PER event happens each time the STURA or STURG instructions are
      used. As they use helpers, we can just save the event in the PER code
      there, if enabled.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2f543949
    • A
      target-s390x: PER storage-alteration event support · 311918b9
      Aurelien Jarno 提交于
      For the PER storage-alteration event we can use the QEMU watchpoint
      infrastructure. When PER is enabled or PER control register changed we
      enable the corresponding watchpoints. When a watchpoint arises we can
      save the event. Unfortunately the current code does not provide the
      address space used to trigger the watchpoint. For now we assume it comes
      from the default ASC.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      311918b9
    • A
      translate-all: fix watchpoints if retranslation not possible · 8d302e76
      Aurelien Jarno 提交于
      The tb_check_watchpoint function currently assumes that all memory
      access is done either directly through the TCG code or through an
      helper which knows its return address. This is obviously wrong as the
      helpers use cpu_ldxx/stxx_data functions to access the memory.
      
      Instead of aborting in that case, don't try to retranslate the code, but
      assume that the CPU state (and especially the program counter) has been
      saved before calling the helper. Then invalidate the TB based on this
      address.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8d302e76
    • A
      target-s390x: PER instruction-fetch event support · f0e0d817
      Aurelien Jarno 提交于
      For the PER instruction-fetch, we can't use the QEMU breakpoint
      infrastructure as it triggers for a single address and not a full
      address range, and as it actually stop before the instruction and
      not before.
      
      We therefore call an helper with the just fetched instruction address,
      which check if the address is within the PER address range. If it is
      the case, an event is recorded and will be signaled through an
      exception.
      
      Note that we implement here the PER-3 behaviour, that is an invalid
      opcode is not considered as an instruction fetch. Without PER-3 this
      behavious is undefined.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f0e0d817