target/riscv: fix vill bit index in vtype register

vill bit is at vtype[XLEN-1]. Signed-off-by: N Frank Chang <frank.chang@sifive.com> Reviewed-by: N Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> Signed-off-by: N Alistair Francis <alistair.francis@wdc.com>

target/riscv: fix vill bit index in vtype register
vill bit is at vtype[XLEN-1]. Signed-off-by: N Frank Chang <frank.chang@sifive.com> Reviewed-by: N Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> Signed-off-by: N Alistair Francis <alistair.francis@wdc.com>
fbcbafa2 · Frank Chang · Alistair Francis · a69f97c1 · fbcbafa2
隐藏空白更改
内联并排

Showing with 1 addition and 1 deletion

target/riscv/cpu.h target/riscv/cpu.h +1 -1

未找到文件。
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
 FIELD(VTYPE, VSEW, 2, 3)
 FIELD(VTYPE, VEDIV, 5, 2)
 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)

 struct CPURISCVState {
    target_ulong gpr[32];