提交 f6737604 编写于 作者: V Vladislav Yasevich 提交者: Michael Roth

rtl8139: Do not consume the packet during overflow in standard mode.

When operation in standard mode, we currently return the size
of packet during buffer overflow.  This consumes the overflow
packet.  Return 0 instead so we can re-process the overflow packet
when we have room.

This fixes issues with lost/dropped fragments of large messages.
Signed-off-by: NVladislav Yasevich <vyasevic@redhat.com>
Reviewed-by: NJason Wang <jasowang@redhat.com>
Message-id: 1441121206-6997-3-git-send-email-vyasevic@redhat.com
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
(cherry picked from commit 26c4e7ca)
*removed dependency on b76f21a7
*removed context dependency on 4cbea598Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
上级 d2b0f96f
...@@ -1159,7 +1159,7 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t ...@@ -1159,7 +1159,7 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t
s->IntrStatus |= RxOverflow; s->IntrStatus |= RxOverflow;
++s->RxMissed; ++s->RxMissed;
rtl8139_update_irq(s); rtl8139_update_irq(s);
return size_; return 0;
} }
packet_header |= RxStatusOK; packet_header |= RxStatusOK;
......
...@@ -56,6 +56,12 @@ static const int tcg_target_call_oarg_regs[1] = { ...@@ -56,6 +56,12 @@ static const int tcg_target_call_oarg_regs[1] = {
#define TCG_REG_TMP TCG_REG_X30 #define TCG_REG_TMP TCG_REG_X30
#ifndef CONFIG_SOFTMMU #ifndef CONFIG_SOFTMMU
/* Note that XZR cannot be encoded in the address base register slot,
as that actaully encodes SP. So if we need to zero-extend the guest
address, via the address index register slot, we need to load even
a zero guest base into a register. */
#define USE_GUEST_BASE (GUEST_BASE != 0 || TARGET_LONG_BITS == 32)
# ifdef CONFIG_USE_GUEST_BASE # ifdef CONFIG_USE_GUEST_BASE
# define TCG_REG_GUEST_BASE TCG_REG_X28 # define TCG_REG_GUEST_BASE TCG_REG_X28
# else # else
...@@ -1216,9 +1222,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, ...@@ -1216,9 +1222,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
s->code_ptr, label_ptr); s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */ #else /* !CONFIG_SOFTMMU */
tcg_out_qemu_ld_direct(s, memop, ext, data_reg, if (USE_GUEST_BASE) {
GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR, tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
otype, addr_reg); TCG_REG_GUEST_BASE, otype, addr_reg);
} else {
tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
}
#endif /* CONFIG_SOFTMMU */ #endif /* CONFIG_SOFTMMU */
} }
...@@ -1238,9 +1248,13 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, ...@@ -1238,9 +1248,13 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
add_qemu_ldst_label(s, false, oi, s_bits == MO_64, data_reg, addr_reg, add_qemu_ldst_label(s, false, oi, s_bits == MO_64, data_reg, addr_reg,
s->code_ptr, label_ptr); s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */ #else /* !CONFIG_SOFTMMU */
tcg_out_qemu_st_direct(s, memop, data_reg, if (USE_GUEST_BASE) {
GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR, tcg_out_qemu_st_direct(s, memop, data_reg,
otype, addr_reg); TCG_REG_GUEST_BASE, otype, addr_reg);
} else {
tcg_out_qemu_st_direct(s, memop, data_reg,
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
}
#endif /* CONFIG_SOFTMMU */ #endif /* CONFIG_SOFTMMU */
} }
...@@ -1795,7 +1809,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) ...@@ -1795,7 +1809,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
CPU_TEMP_BUF_NLONGS * sizeof(long)); CPU_TEMP_BUF_NLONGS * sizeof(long));
#if defined(CONFIG_USE_GUEST_BASE) #if defined(CONFIG_USE_GUEST_BASE)
if (GUEST_BASE) { if (USE_GUEST_BASE) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, GUEST_BASE); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, GUEST_BASE);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
} }
......
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