Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu
提交 f044ac49 编写于 作者: J Jean-Christophe Dubois 提交者： Peter Maydell
浏览文件
操作

i.MX: KZM: use standalone i.MX31 SOC support 

Convert the KZM board to use the i.MX31 SoC defintition instead of
redefining the entire SoC on the machine level. Major rewrite of the
machine init code.

While touching the memory map comment de-indent to the correct level
of indentation.

This obsoletes the legacy i.MX device device creation helpers which are removed.

Tested by booting a minimal Linux system on the emulated platform
Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 5e783561f092e1c939562fdff001f1ab1194b07f.1441057361.git.jcd@tribudubois.net
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
上级 558df83d
隐藏空白更改
内联 并排
Showing with 102 addition and 186 deletion
hw/arm/kzm.c
浏览文件 @ f044ac49
......@@ -13,131 +13,130 @@
* i.MX31 SoC
*/
#include "hw/sysbus.h"
#include "hw/arm/fsl-imx31.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "hw/hw.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/devices.h"
#include "hw/char/serial.h"
#include "hw/intc/imx_avic.h"
#include "hw/arm/imx.h"
/* Memory map for Kzm Emulation Baseboard:
* 0x00000000-0x00003fff 16k secure ROM IGNORED
* 0x00004000-0x00407fff Reserved IGNORED
* 0x00404000-0x00407fff ROM IGNORED
* 0x00408000-0x0fffffff Reserved IGNORED
* 0x10000000-0x1fffbfff RAM aliasing IGNORED
* 0x1fffc000-0x1fffffff RAM EMULATED
* 0x20000000-0x2fffffff Reserved IGNORED
* 0x30000000-0x7fffffff I.MX31 Internal Register Space
* 0x43f00000 IO_AREA0
* 0x43f90000 UART1 EMULATED
* 0x43f94000 UART2 EMULATED
* 0x68000000 AVIC EMULATED
* 0x53f80000 CCM EMULATED
* 0x53f94000 PIT 1 EMULATED
* 0x53f98000 PIT 2 EMULATED
* 0x53f90000 GPT EMULATED
* 0x80000000-0x87ffffff RAM EMULATED
* 0x88000000-0x8fffffff RAM Aliasing EMULATED
* 0xa0000000-0xafffffff NAND Flash IGNORED
* 0xb0000000-0xb3ffffff Unavailable IGNORED
* 0xb4000000-0xb4000fff 8-bit free space IGNORED
* 0xb4001000-0xb400100f Board control IGNORED
* 0xb4001003 DIP switch
* 0xb4001010-0xb400101f 7-segment LED IGNORED
* 0xb4001020-0xb400102f LED IGNORED
* 0xb4001030-0xb400103f LED IGNORED
* 0xb4001040-0xb400104f FPGA, UART EMULATED
* 0xb4001050-0xb400105f FPGA, UART EMULATED
* 0xb4001060-0xb40fffff FPGA IGNORED
* 0xb6000000-0xb61fffff LAN controller EMULATED
* 0xb6200000-0xb62fffff FPGA NAND Controller IGNORED
* 0xb6300000-0xb7ffffff Free IGNORED
* 0xb8000000-0xb8004fff Memory control registers IGNORED
* 0xc0000000-0xc3ffffff PCMCIA/CF IGNORED
* 0xc4000000-0xffffffff Reserved IGNORED
*/
#define KZM_RAMADDRESS (0x80000000)
#define KZM_FPGA (0xb4001040)
#include "sysemu/qtest.h"
/* Memory map for Kzm Emulation Baseboard:
* 0x00000000-0x7fffffff See i.MX31 SOC for support
* 0x80000000-0x8fffffff RAM EMULATED
* 0x90000000-0x9fffffff RAM EMULATED
* 0xa0000000-0xafffffff Flash IGNORED
* 0xb0000000-0xb3ffffff Unavailable IGNORED
* 0xb4000000-0xb4000fff 8-bit free space IGNORED
* 0xb4001000-0xb400100f Board control IGNORED
* 0xb4001003 DIP switch
* 0xb4001010-0xb400101f 7-segment LED IGNORED
* 0xb4001020-0xb400102f LED IGNORED
* 0xb4001030-0xb400103f LED IGNORED
* 0xb4001040-0xb400104f FPGA, UART EMULATED
* 0xb4001050-0xb400105f FPGA, UART EMULATED
* 0xb4001060-0xb40fffff FPGA IGNORED
* 0xb6000000-0xb61fffff LAN controller EMULATED
* 0xb6200000-0xb62fffff FPGA NAND Controller IGNORED
* 0xb6300000-0xb7ffffff Free IGNORED
* 0xb8000000-0xb8004fff Memory control registers IGNORED
* 0xc0000000-0xc3ffffff PCMCIA/CF IGNORED
* 0xc4000000-0xffffffff Reserved IGNORED
*/
typedef struct IMX31KZM {
FslIMX31State soc;
MemoryRegion ram;
MemoryRegion ram_alias;
} IMX31KZM;
#define KZM_RAM_ADDR (FSL_IMX31_SDRAM0_ADDR)
#define KZM_FPGA_ADDR (FSL_IMX31_CS4_ADDR + 0x1040)
#define KZM_LAN9118_ADDR (FSL_IMX31_CS5_ADDR)
static struct arm_boot_info kzm_binfo = {
.loader_start = KZM_RAMADDRESS,
.loader_start = KZM_RAM_ADDR,
.board_id = 1722,
};
static void kzm_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
DeviceState *dev;
DeviceState *ccm;
if (!cpu_model) {
cpu_model = "arm1136";
}
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
IMX31KZM *s = g_new0(IMX31KZM, 1);
Error *err = NULL;
unsigned int ram_size;
unsigned int alias_offset;
unsigned int i;
object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX31);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
/* On a real system, the first 16k is a `secure boot rom' */
memory_region_allocate_system_memory(ram, NULL, "kzm.ram", ram_size);
memory_region_add_subregion(address_space_mem, KZM_RAMADDRESS, ram);
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x88000000, ram_alias);
memory_region_init_ram(sram, NULL, "kzm.sram", 0x4000, &error_abort);
memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);
dev = sysbus_create_varargs(TYPE_IMX_AVIC, 0x68000000,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
NULL);
imx_serial_create(0, 0x43f90000, qdev_get_gpio_in(dev, 45));
imx_serial_create(1, 0x43f94000, qdev_get_gpio_in(dev, 32));
ccm = sysbus_create_simple(TYPE_IMX_CCM, 0x53f80000, NULL);
/* Check the amount of memory is compatible with the SOC */
if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {
error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
"reduced to %x", machine->ram_size,
FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE);
machine->ram_size = FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE;
}
imx_timerp_create(0x53f94000, qdev_get_gpio_in(dev, 28), ccm);
imx_timerp_create(0x53f98000, qdev_get_gpio_in(dev, 27), ccm);
imx_timerg_create(0x53f90000, qdev_get_gpio_in(dev, 29), ccm);
memory_region_allocate_system_memory(&s->ram, NULL, "kzm.ram",
machine->ram_size);
memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR,
&s->ram);
/* initialize the alias memory if any */
for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
(i < 2) && ram_size; i++) {
unsigned int size;
static const struct {
hwaddr addr;
unsigned int size;
} ram[2] = {
{ FSL_IMX31_SDRAM0_ADDR, FSL_IMX31_SDRAM0_SIZE },
{ FSL_IMX31_SDRAM1_ADDR, FSL_IMX31_SDRAM1_SIZE },
};
size = MIN(ram_size, ram[i].size);
ram_size -= size;
if (size < ram[i].size) {
memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
&s->ram, alias_offset, ram[i].size - size);
memory_region_add_subregion(get_system_memory(),
ram[i].addr + size, &s->ram_alias);
}
alias_offset += ram[i].size;
}
if (nd_table[0].used) {
lan9118_init(&nd_table[0], 0xb6000000, qdev_get_gpio_in(dev, 52));
lan9118_init(&nd_table[0], KZM_LAN9118_ADDR,
qdev_get_gpio_in(DEVICE(&s->soc.avic), 52));
}
if (serial_hds[2]) { /* touchscreen */
serial_mm_init(address_space_mem, KZM_FPGA+0x10, 0,
qdev_get_gpio_in(dev, 52),
14745600, serial_hds[2],
DEVICE_NATIVE_ENDIAN);
serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0,
qdev_get_gpio_in(DEVICE(&s->soc.avic), 52),
14745600, serial_hds[2], DEVICE_NATIVE_ENDIAN);
}
kzm_binfo.ram_size = ram_size;
kzm_binfo.kernel_filename = kernel_filename;
kzm_binfo.kernel_cmdline = kernel_cmdline;
kzm_binfo.initrd_filename = initrd_filename;
kzm_binfo.ram_size = machine->ram_size;
kzm_binfo.kernel_filename = machine->kernel_filename;
kzm_binfo.kernel_cmdline = machine->kernel_cmdline;
kzm_binfo.initrd_filename = machine->initrd_filename;
kzm_binfo.nb_cpus = 1;
arm_load_kernel(cpu, &kzm_binfo);
if (!qtest_enabled()) {
arm_load_kernel(&s->soc.cpu, &kzm_binfo);
}
}
static QEMUMachine kzm_machine = {
......
hw/char/imx_serial.c
浏览文件 @ f044ac49
......@@ -21,7 +21,6 @@
#include "hw/char/imx_serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
#include "hw/arm/imx.h"
//#define DEBUG_SERIAL 1
#ifdef DEBUG_SERIAL
......@@ -334,40 +333,6 @@ static void imx_serial_init(Object *obj)
sysbus_init_irq(sbd, &s->irq);
}
void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *bus;
CharDriverState *chr;
const char chr_name[] = "serial";
char label[ARRAY_SIZE(chr_name) + 1];
dev = qdev_create(NULL, TYPE_IMX_SERIAL);
if (uart >= MAX_SERIAL_PORTS) {
hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
uart, MAX_SERIAL_PORTS);
}
chr = serial_hds[uart];
if (!chr) {
snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
chr = qemu_chr_new(label, "null", NULL);
if (!(chr)) {
hw_error("Can't assign serial port to imx-uart%d.\n", uart);
}
}
qdev_prop_set_chr(dev, "chardev", chr);
bus = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);
}
static Property imx_serial_properties[] = {
DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
DEFINE_PROP_END_OF_LIST(),
......
hw/timer/imx_epit.c
浏览文件 @ f044ac49
......@@ -12,7 +12,6 @@
*
*/
#include "hw/arm/imx.h"
#include "hw/timer/imx_epit.h"
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
......@@ -287,16 +286,6 @@ static void imx_epit_cmp(void *opaque)
imx_epit_update_int(s);
}
void imx_timerp_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
{
IMXEPITState *pp;
DeviceState *dev;
dev = sysbus_create_simple(TYPE_IMX_EPIT, addr, irq);
pp = IMX_EPIT(dev);
pp->ccm = ccm;
}
static const MemoryRegionOps imx_epit_ops = {
.read = imx_epit_read,
.write = imx_epit_write,
......
hw/timer/imx_gpt.c
浏览文件 @ f044ac49
......@@ -12,7 +12,6 @@
*
*/
#include "hw/arm/imx.h"
#include "hw/timer/imx_gpt.h"
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
......@@ -449,16 +448,6 @@ static void imx_gpt_realize(DeviceState *dev, Error **errp)
s->timer = ptimer_init(bh);
}
void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
{
IMXGPTState *pp;
DeviceState *dev;
dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq);
pp = IMX_GPT(dev);
pp->ccm = ccm;
}
static void imx_gpt_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
......
include/hw/arm/imx.h 已删除 100644 → 0
浏览文件 @ 558df83d
/*
* i.MX31 emulation
*
* Copyright (C) 2012 Peter Chubb
* NICTA
*
* This code is released under the GPL, version 2.0 or later
* See the file `../COPYING' for details.
*/
#ifndef IMX_H
#define IMX_H
#include "hw/misc/imx_ccm.h"
void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
#endif /* IMX_H */
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或