提交 e49798b1 编写于 作者: A Alexander Graf

openpic: export e500 epr enable into a ppc.c function

Enabling and disabling the EPR capability (mpic_proxy) is a system
wide operation. As such, it belongs into the ppc.c file, since that's
where PPC specific machine wide logic happens.
Signed-off-by: NAlexander Graf <agraf@suse.de>
上级 d3dccee1
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#include "sysbus.h" #include "sysbus.h"
#include "pci/msi.h" #include "pci/msi.h"
#include "qemu/bitops.h" #include "qemu/bitops.h"
#include "ppc.h"
//#define DEBUG_OPENPIC //#define DEBUG_OPENPIC
...@@ -646,8 +647,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) ...@@ -646,8 +647,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
static void openpic_gcr_write(OpenPICState *opp, uint64_t val) static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
{ {
CPUArchState *env; bool mpic_proxy = false;
int mpic_proxy = 0;
if (val & GCR_RESET) { if (val & GCR_RESET) {
openpic_reset(&opp->busdev.qdev); openpic_reset(&opp->busdev.qdev);
...@@ -659,11 +659,10 @@ static void openpic_gcr_write(OpenPICState *opp, uint64_t val) ...@@ -659,11 +659,10 @@ static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
/* Set external proxy mode */ /* Set external proxy mode */
if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
mpic_proxy = 1; mpic_proxy = true;
}
for (env = first_cpu; env != NULL; env = env->next_cpu) {
env->mpic_proxy = mpic_proxy;
} }
ppce500_set_mpic_proxy(mpic_proxy);
} }
static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
......
...@@ -428,6 +428,17 @@ void ppce500_irq_init(CPUPPCState *env) ...@@ -428,6 +428,17 @@ void ppce500_irq_init(CPUPPCState *env)
env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
cpu, PPCE500_INPUT_NB); cpu, PPCE500_INPUT_NB);
} }
/* Enable or Disable the E500 EPR capability */
void ppce500_set_mpic_proxy(bool enabled)
{
CPUPPCState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
env->mpic_proxy = enabled;
}
}
/*****************************************************************************/ /*****************************************************************************/
/* PowerPC time base and decrementer emulation */ /* PowerPC time base and decrementer emulation */
......
...@@ -73,6 +73,8 @@ void ppc6xx_irq_init (CPUPPCState *env); ...@@ -73,6 +73,8 @@ void ppc6xx_irq_init (CPUPPCState *env);
void ppc970_irq_init (CPUPPCState *env); void ppc970_irq_init (CPUPPCState *env);
void ppcPOWER7_irq_init (CPUPPCState *env); void ppcPOWER7_irq_init (CPUPPCState *env);
void ppce500_set_mpic_proxy(bool enabled);
/* PPC machines for OpenBIOS */ /* PPC machines for OpenBIOS */
enum { enum {
ARCH_PREP = 0, ARCH_PREP = 0,
......
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