Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu
提交 e3afa1c4 编写于 作者: R Richard Henderson
浏览文件
操作

tcg-ia64: Use TCGMemOp within qemu_ldst routines 

Acked-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>
上级 5c5432e7
隐藏空白更改
内联 并排
Showing with 91 addition and 82 deletion
tcg/ia64/tcg-target.c
浏览文件 @ e3afa1c4
...@@ -1496,7 +1496,7 @@ static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, ...@@ -1496,7 +1496,7 @@ static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
R2 is loaded with the address of the addend TLB entry. R2 is loaded with the address of the addend TLB entry.
R57 is loaded with the address, zero extented on 32-bit targets. */ R57 is loaded with the address, zero extented on 32-bit targets. */
static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
int s_bits, uint64_t offset_rw, TCGMemOp s_bits, uint64_t offset_rw,
uint64_t offset_addend) uint64_t offset_addend)
{ {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
...@@ -1538,23 +1538,24 @@ static const void * const qemu_ld_helpers[4] = { ...@@ -1538,23 +1538,24 @@ static const void * const qemu_ld_helpers[4] = {
helper_ldq_mmu, helper_ldq_mmu,
}; };
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
TCGMemOp opc)
{ {
int addr_reg, data_reg, mem_index, s_bits, bswap; static const uint64_t opc_ld_m1[4] = {
uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 }; OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, };
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 }; static const uint64_t opc_ext_i29[8] = {
OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
};
int addr_reg, data_reg, mem_index;
TCGMemOp s_bits, bswap;
data_reg = *args++; data_reg = *args++;
addr_reg = *args++; addr_reg = *args++;
mem_index = *args; mem_index = *args;
s_bits = opc & 3; s_bits = opc & MO_SIZE;
bswap = opc & MO_BSWAP;
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
/* Read the TLB entry */ /* Read the TLB entry */
tcg_out_qemu_tlb(s, addr_reg, s_bits, tcg_out_qemu_tlb(s, addr_reg, s_bits,
...@@ -1575,14 +1576,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1575,14 +1576,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
TCG_REG_R3, TCG_REG_R57), TCG_REG_R3, TCG_REG_R57),
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0)); TCG_REG_R3, 0));
if (bswap && s_bits == 1) { if (bswap && s_bits == MO_16) {
tcg_out_bundle(s, MmI, tcg_out_bundle(s, MmI,
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
TCG_REG_R8, TCG_REG_R3), TCG_REG_R8, TCG_REG_R3),
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
TCG_REG_R8, TCG_REG_R8, 15, 15)); TCG_REG_R8, TCG_REG_R8, 15, 15));
} else if (bswap && s_bits == 2) { } else if (bswap && s_bits == MO_32) {
tcg_out_bundle(s, MmI, tcg_out_bundle(s, MmI,
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
TCG_REG_R8, TCG_REG_R3), TCG_REG_R8, TCG_REG_R3),
...@@ -1596,7 +1597,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1596,7 +1597,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} }
if (!bswap || s_bits == 0) { if (!bswap) {
tcg_out_bundle(s, miB, tcg_out_bundle(s, miB,
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
mem_index, TCG_REG_R0), mem_index, TCG_REG_R0),
...@@ -1613,7 +1614,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1613,7 +1614,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
TCG_REG_B0, TCG_REG_B6)); TCG_REG_B0, TCG_REG_B6));
} }
if (opc == 3) { if (s_bits == MO_64) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
...@@ -1623,7 +1624,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1623,7 +1624,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc], tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
data_reg, TCG_REG_R8)); data_reg, TCG_REG_R8));
} }
} }
...@@ -1637,22 +1638,21 @@ static const void * const qemu_st_helpers[4] = { ...@@ -1637,22 +1638,21 @@ static const void * const qemu_st_helpers[4] = {
helper_stq_mmu, helper_stq_mmu,
}; };
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
TCGMemOp opc)
{ {
int addr_reg, data_reg, mem_index, bswap; static const uint64_t opc_st_m4[4] = {
uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 }; OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
};
int addr_reg, data_reg, mem_index;
TCGMemOp s_bits;
data_reg = *args++; data_reg = *args++;
addr_reg = *args++; addr_reg = *args++;
mem_index = *args; mem_index = *args;
s_bits = opc & MO_SIZE;
#ifdef TARGET_WORDS_BIGENDIAN tcg_out_qemu_tlb(s, addr_reg, s_bits,
bswap = 1;
#else
bswap = 0;
#endif
tcg_out_qemu_tlb(s, addr_reg, opc,
offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
offsetof(CPUArchState, tlb_table[mem_index][0].addend)); offsetof(CPUArchState, tlb_table[mem_index][0].addend));
...@@ -1660,9 +1660,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1660,9 +1660,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_bundle(s, mLX, tcg_out_bundle(s, mLX,
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
TCG_REG_R56, 0, TCG_AREG0), TCG_REG_R56, 0, TCG_AREG0),
tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]), tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
(tcg_target_long) qemu_st_helpers[opc])); (tcg_target_long) qemu_st_helpers[s_bits]));
tcg_out_bundle(s, MmI, tcg_out_bundle(s, MmI,
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
TCG_REG_R2, 8), TCG_REG_R2, 8),
...@@ -1671,14 +1671,20 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1671,14 +1671,20 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0)); TCG_REG_R3, 0));
if (!bswap || opc == 0) { switch (opc) {
case MO_8:
case MO_16:
case MO_32:
case MO_64:
tcg_out_bundle(s, mii, tcg_out_bundle(s, mii,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2), TCG_REG_R1, TCG_REG_R2),
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
0, data_reg), 0, data_reg),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} else if (opc == 1) { break;
case MO_16 | MO_BSWAP:
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2), TCG_REG_R1, TCG_REG_R2),
...@@ -1692,7 +1698,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1692,7 +1698,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, TCG_REG_R2, 0xb)); TCG_REG_R2, TCG_REG_R2, 0xb));
data_reg = TCG_REG_R2; data_reg = TCG_REG_R2;
} else if (opc == 2) { break;
case MO_32 | MO_BSWAP:
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2), TCG_REG_R1, TCG_REG_R2),
...@@ -1706,7 +1714,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1706,7 +1714,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, TCG_REG_R2, 0xb)); TCG_REG_R2, TCG_REG_R2, 0xb));
data_reg = TCG_REG_R2; data_reg = TCG_REG_R2;
} else if (opc == 3) { break;
case MO_64 | MO_BSWAP:
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2), TCG_REG_R1, TCG_REG_R2),
...@@ -1715,10 +1725,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1715,10 +1725,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, data_reg, 0xb)); TCG_REG_R2, data_reg, 0xb));
data_reg = TCG_REG_R2; data_reg = TCG_REG_R2;
break;
default:
tcg_abort();
} }
tcg_out_bundle(s, miB, tcg_out_bundle(s, miB,
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc], tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
data_reg, TCG_REG_R3), data_reg, TCG_REG_R3),
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59, tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
mem_index, TCG_REG_R0), mem_index, TCG_REG_R0),
...@@ -1728,7 +1742,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1728,7 +1742,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
#else /* !CONFIG_SOFTMMU */ #else /* !CONFIG_SOFTMMU */
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
TCGMemOp opc)
{ {
static uint64_t const opc_ld_m1[4] = { static uint64_t const opc_ld_m1[4] = {
OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
...@@ -1736,17 +1751,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1736,17 +1751,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
static uint64_t const opc_sxt_i29[4] = { static uint64_t const opc_sxt_i29[4] = {
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
}; };
int addr_reg, data_reg, s_bits, bswap; int addr_reg, data_reg;
TCGMemOp s_bits, bswap;
data_reg = *args++; data_reg = *args++;
addr_reg = *args++; addr_reg = *args++;
s_bits = opc & 3; s_bits = opc & MO_SIZE;
bswap = opc & MO_BSWAP;
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
#if TARGET_LONG_BITS == 32 #if TARGET_LONG_BITS == 32
if (GUEST_BASE != 0) { if (GUEST_BASE != 0) {
...@@ -1764,8 +1775,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1764,8 +1775,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} }
if (!bswap || s_bits == 0) { if (!bswap) {
if (s_bits == opc) { if (!(opc & MO_SIGN)) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
data_reg, TCG_REG_R2), data_reg, TCG_REG_R2),
...@@ -1779,7 +1790,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1779,7 +1790,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
data_reg, data_reg)); data_reg, data_reg));
} }
} else if (s_bits == 3) { } else if (s_bits == MO_64) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
data_reg, TCG_REG_R2), data_reg, TCG_REG_R2),
...@@ -1787,7 +1798,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1787,7 +1798,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
data_reg, data_reg, 0xb)); data_reg, data_reg, 0xb));
} else { } else {
if (s_bits == 1) { if (s_bits == MO_16) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
data_reg, TCG_REG_R2), data_reg, TCG_REG_R2),
...@@ -1802,7 +1813,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1802,7 +1813,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
data_reg, data_reg, 31, 31)); data_reg, data_reg, 31, 31));
} }
if (opc == s_bits) { if (!(opc & MO_SIGN)) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
...@@ -1833,28 +1844,28 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1833,28 +1844,28 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} }
if (bswap && s_bits == 1) { if (bswap && s_bits == MO_16) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
data_reg, data_reg, 15, 15), data_reg, data_reg, 15, 15),
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
data_reg, data_reg, 0xb)); data_reg, data_reg, 0xb));
} else if (bswap && s_bits == 2) { } else if (bswap && s_bits == MO_32) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
data_reg, data_reg, 31, 31), data_reg, data_reg, 31, 31),
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
data_reg, data_reg, 0xb)); data_reg, data_reg, 0xb));
} else if (bswap && s_bits == 3) { } else if (bswap && s_bits == MO_64) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
data_reg, data_reg, 0xb)); data_reg, data_reg, 0xb));
} }
if (s_bits != opc) { if (opc & MO_SIGN) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
...@@ -1864,24 +1875,22 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) ...@@ -1864,24 +1875,22 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
#endif #endif
} }
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
TCGMemOp opc)
{ {
static uint64_t const opc_st_m4[4] = { static uint64_t const opc_st_m4[4] = {
OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
}; };
int addr_reg, data_reg, bswap; int addr_reg, data_reg;
#if TARGET_LONG_BITS == 64 #if TARGET_LONG_BITS == 64
uint64_t add_guest_base; uint64_t add_guest_base;
#endif #endif
TCGMemOp s_bits, bswap;
data_reg = *args++; data_reg = *args++;
addr_reg = *args++; addr_reg = *args++;
s_bits = opc & MO_SIZE;
#ifdef TARGET_WORDS_BIGENDIAN bswap = opc & MO_BSWAP;
bswap = 1;
#else
bswap = 0;
#endif
#if TARGET_LONG_BITS == 32 #if TARGET_LONG_BITS == 32
if (GUEST_BASE != 0) { if (GUEST_BASE != 0) {
...@@ -1900,7 +1909,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1900,7 +1909,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
} }
if (bswap) { if (bswap) {
if (opc == 1) { if (s_bits == MO_16) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
...@@ -1908,7 +1917,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1908,7 +1917,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
TCG_REG_R3, TCG_REG_R3, 0xb)); TCG_REG_R3, TCG_REG_R3, 0xb));
data_reg = TCG_REG_R3; data_reg = TCG_REG_R3;
} else if (opc == 2) { } else if (s_bits == MO_32) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
...@@ -1916,7 +1925,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1916,7 +1925,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
TCG_REG_R3, TCG_REG_R3, 0xb)); TCG_REG_R3, TCG_REG_R3, 0xb));
data_reg = TCG_REG_R3; data_reg = TCG_REG_R3;
} else if (opc == 3) { } else if (s_bits == MO_64) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
...@@ -1926,7 +1935,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1926,7 +1935,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
} }
} }
tcg_out_bundle(s, mmI, tcg_out_bundle(s, mmI,
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
data_reg, TCG_REG_R2), data_reg, TCG_REG_R2),
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
...@@ -1939,14 +1948,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1939,14 +1948,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0); add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
} }
if (!bswap || opc == 0) { if (!bswap) {
tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
add_guest_base, add_guest_base,
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
data_reg, addr_reg), data_reg, addr_reg),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} else { } else {
if (opc == 1) { if (s_bits == MO_16) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
add_guest_base, add_guest_base,
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
...@@ -1954,7 +1963,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1954,7 +1963,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
TCG_REG_R3, TCG_REG_R3, 0xb)); TCG_REG_R3, TCG_REG_R3, 0xb));
data_reg = TCG_REG_R3; data_reg = TCG_REG_R3;
} else if (opc == 2) { } else if (s_bits == MO_32) {
tcg_out_bundle(s, mII, tcg_out_bundle(s, mII,
add_guest_base, add_guest_base,
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
...@@ -1962,7 +1971,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1962,7 +1971,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
TCG_REG_R3, TCG_REG_R3, 0xb)); TCG_REG_R3, TCG_REG_R3, 0xb));
data_reg = TCG_REG_R3; data_reg = TCG_REG_R3;
} else if (opc == 3) { } else if (s_bits == MO_64) {
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
add_guest_base, add_guest_base,
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
...@@ -1971,7 +1980,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) ...@@ -1971,7 +1980,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
data_reg = TCG_REG_R3; data_reg = TCG_REG_R3;
} }
tcg_out_bundle(s, miI, tcg_out_bundle(s, miI,
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
data_reg, addr_reg), data_reg, addr_reg),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
...@@ -2203,39 +2212,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, ...@@ -2203,39 +2212,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break; break;
case INDEX_op_qemu_ld8u: case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0); tcg_out_qemu_ld(s, args, MO_UB);
break; break;
case INDEX_op_qemu_ld8s: case INDEX_op_qemu_ld8s:
tcg_out_qemu_ld(s, args, 0 | 4); tcg_out_qemu_ld(s, args, MO_SB);
break; break;
case INDEX_op_qemu_ld16u: case INDEX_op_qemu_ld16u:
tcg_out_qemu_ld(s, args, 1); tcg_out_qemu_ld(s, args, MO_TEUW);
break; break;
case INDEX_op_qemu_ld16s: case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4); tcg_out_qemu_ld(s, args, MO_TESW);
break; break;
case INDEX_op_qemu_ld32: case INDEX_op_qemu_ld32:
case INDEX_op_qemu_ld32u: case INDEX_op_qemu_ld32u:
tcg_out_qemu_ld(s, args, 2); tcg_out_qemu_ld(s, args, MO_TEUL);
break; break;
case INDEX_op_qemu_ld32s: case INDEX_op_qemu_ld32s:
tcg_out_qemu_ld(s, args, 2 | 4); tcg_out_qemu_ld(s, args, MO_TESL);
break; break;
case INDEX_op_qemu_ld64: case INDEX_op_qemu_ld64:
tcg_out_qemu_ld(s, args, 3); tcg_out_qemu_ld(s, args, MO_TEQ);
break; break;
case INDEX_op_qemu_st8: case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0); tcg_out_qemu_st(s, args, MO_UB);
break; break;
case INDEX_op_qemu_st16: case INDEX_op_qemu_st16:
tcg_out_qemu_st(s, args, 1); tcg_out_qemu_st(s, args, MO_TEUW);
break; break;
case INDEX_op_qemu_st32: case INDEX_op_qemu_st32:
tcg_out_qemu_st(s, args, 2); tcg_out_qemu_st(s, args, MO_TEUL);
break; break;
case INDEX_op_qemu_st64: case INDEX_op_qemu_st64:
tcg_out_qemu_st(s, args, 3); tcg_out_qemu_st(s, args, MO_TEQ);
break; break;
default: default:
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或