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d87aaf93
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体验新版 GitCode,发现更多精彩内容 >>
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d87aaf93
编写于
9月 25, 2012
作者:
R
Richard Henderson
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL
Signed-off-by:
N
Richard Henderson
<
rth@twiddle.net
>
上级
d1c04a2b
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
32 addition
and
57 deletion
+32
-57
target-s390x/insn-data.def
target-s390x/insn-data.def
+7
-0
target-s390x/translate.c
target-s390x/translate.c
+25
-57
未找到文件。
target-s390x/insn-data.def
浏览文件 @
d87aaf93
...
@@ -41,12 +41,19 @@
...
@@ -41,12 +41,19 @@
C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
/* MULTIPLY */
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
C(0xe35c, MFY, RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
/* MULTIPLY HALFWORD */
/* MULTIPLY HALFWORD */
C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
/* MULTIPLY HALFWORD IMMEDIATE */
/* MULTIPLY HALFWORD IMMEDIATE */
C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0)
C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0)
C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0)
C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0)
/* MULTIPLY LOGICAL */
C(0xb996, MLR, RRE, Z, r1p1_32u, r2_32u, new, r1_D32, mul, 0)
C(0xe396, ML, RXY_a, Z, r1p1_32u, m2_32u, new, r1_D32, mul, 0)
/* MULTIPLY SINGLE */
/* MULTIPLY SINGLE */
C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0)
C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0)
C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0)
C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0)
...
...
target-s390x/translate.c
浏览文件 @
d87aaf93
...
@@ -1624,18 +1624,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
...
@@ -1624,18 +1624,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
store_reg32_i64
(
r1
,
tmp2
);
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i64
(
tmp2
);
break
;
break
;
case
0x96
:
/* ML R1,D2(X2,B2) [RXY] */
tmp2
=
tcg_temp_new_i64
();
tmp3
=
load_reg
((
r1
+
1
)
&
15
);
tcg_gen_ext32u_i64
(
tmp3
,
tmp3
);
tcg_gen_qemu_ld32u
(
tmp2
,
addr
,
get_mem_index
(
s
));
tcg_gen_mul_i64
(
tmp2
,
tmp2
,
tmp3
);
store_reg32_i64
((
r1
+
1
)
&
15
,
tmp2
);
tcg_gen_shri_i64
(
tmp2
,
tmp2
,
32
);
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i64
(
tmp3
);
break
;
case
0x97
:
/* DL R1,D2(X2,B2) [RXY] */
case
0x97
:
/* DL R1,D2(X2,B2) [RXY] */
/* reg(r1) = reg(r1, r1+1) % ld32(addr) */
/* reg(r1) = reg(r1, r1+1) % ld32(addr) */
/* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
/* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
...
@@ -3219,19 +3207,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
...
@@ -3219,19 +3207,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
store_reg32
(
r1
,
tmp32_1
);
store_reg32
(
r1
,
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
break
;
break
;
case
0x96
:
/* MLR R1,R2 [RRE] */
/* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
tmp2
=
load_reg
(
r2
);
tmp3
=
load_reg
((
r1
+
1
)
&
15
);
tcg_gen_ext32u_i64
(
tmp2
,
tmp2
);
tcg_gen_ext32u_i64
(
tmp3
,
tmp3
);
tcg_gen_mul_i64
(
tmp2
,
tmp2
,
tmp3
);
store_reg32_i64
((
r1
+
1
)
&
15
,
tmp2
);
tcg_gen_shri_i64
(
tmp2
,
tmp2
,
32
);
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i64
(
tmp3
);
break
;
case
0x97
:
/* DLR R1,R2 [RRE] */
case
0x97
:
/* DLR R1,R2 [RRE] */
/* reg(r1) = reg(r1, r1+1) % reg(r2) */
/* reg(r1) = reg(r1, r1+1) % reg(r2) */
/* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
/* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
...
@@ -3605,21 +3580,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
...
@@ -3605,21 +3580,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
break
;
case
0x1c
:
/* MR R1,R2 [RR] */
/* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
insn
=
ld_code2
(
env
,
s
->
pc
);
decode_rr
(
s
,
insn
,
&
r1
,
&
r2
);
tmp2
=
load_reg
(
r2
);
tmp3
=
load_reg
((
r1
+
1
)
&
15
);
tcg_gen_ext32s_i64
(
tmp2
,
tmp2
);
tcg_gen_ext32s_i64
(
tmp3
,
tmp3
);
tcg_gen_mul_i64
(
tmp2
,
tmp2
,
tmp3
);
store_reg32_i64
((
r1
+
1
)
&
15
,
tmp2
);
tcg_gen_shri_i64
(
tmp2
,
tmp2
,
32
);
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i64
(
tmp3
);
break
;
case
0x1d
:
/* DR R1,R2 [RR] */
case
0x1d
:
/* DR R1,R2 [RR] */
insn
=
ld_code2
(
env
,
s
->
pc
);
insn
=
ld_code2
(
env
,
s
->
pc
);
decode_rr
(
s
,
insn
,
&
r1
,
&
r2
);
decode_rr
(
s
,
insn
,
&
r1
,
&
r2
);
...
@@ -3855,23 +3815,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
...
@@ -3855,23 +3815,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
break
;
case
0x5c
:
/* M R1,D2(X2,B2) [RX] */
/* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
insn
=
ld_code4
(
env
,
s
->
pc
);
tmp
=
decode_rx
(
s
,
insn
,
&
r1
,
&
x2
,
&
b2
,
&
d2
);
tmp2
=
tcg_temp_new_i64
();
tcg_gen_qemu_ld32s
(
tmp2
,
tmp
,
get_mem_index
(
s
));
tmp3
=
load_reg
((
r1
+
1
)
&
15
);
tcg_gen_ext32s_i64
(
tmp2
,
tmp2
);
tcg_gen_ext32s_i64
(
tmp3
,
tmp3
);
tcg_gen_mul_i64
(
tmp2
,
tmp2
,
tmp3
);
store_reg32_i64
((
r1
+
1
)
&
15
,
tmp2
);
tcg_gen_shri_i64
(
tmp2
,
tmp2
,
32
);
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i64
(
tmp3
);
break
;
case
0x5d
:
/* D R1,D2(X2,B2) [RX] */
case
0x5d
:
/* D R1,D2(X2,B2) [RX] */
insn
=
ld_code4
(
env
,
s
->
pc
);
insn
=
ld_code4
(
env
,
s
->
pc
);
tmp3
=
decode_rx
(
s
,
insn
,
&
r1
,
&
x2
,
&
b2
,
&
d2
);
tmp3
=
decode_rx
(
s
,
insn
,
&
r1
,
&
x2
,
&
b2
,
&
d2
);
...
@@ -4868,6 +4811,15 @@ static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
...
@@ -4868,6 +4811,15 @@ static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
store_reg32_i64
(
get_field
(
f
,
r1
),
o
->
out
);
store_reg32_i64
(
get_field
(
f
,
r1
),
o
->
out
);
}
}
static
void
wout_r1_D32
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
{
/* ??? Specification exception: r1 must be even. */
int
r1
=
get_field
(
f
,
r1
);
store_reg32_i64
((
r1
+
1
)
&
15
,
o
->
out
);
tcg_gen_shri_i64
(
o
->
out
,
o
->
out
,
32
);
store_reg32_i64
(
r1
,
o
->
out
);
}
static
void
wout_m1_32
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
static
void
wout_m1_32
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
{
{
tcg_gen_qemu_st32
(
o
->
out
,
o
->
addr1
,
get_mem_index
(
s
));
tcg_gen_qemu_st32
(
o
->
out
,
o
->
addr1
,
get_mem_index
(
s
));
...
@@ -4892,6 +4844,22 @@ static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
...
@@ -4892,6 +4844,22 @@ static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
o
->
g_in1
=
true
;
o
->
g_in1
=
true
;
}
}
static
void
in1_r1p1_32s
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
{
/* ??? Specification exception: r1 must be even. */
int
r1
=
get_field
(
f
,
r1
);
o
->
in1
=
tcg_temp_new_i64
();
tcg_gen_ext32s_i64
(
o
->
in1
,
regs
[(
r1
+
1
)
&
15
]);
}
static
void
in1_r1p1_32u
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
{
/* ??? Specification exception: r1 must be even. */
int
r1
=
get_field
(
f
,
r1
);
o
->
in1
=
tcg_temp_new_i64
();
tcg_gen_ext32u_i64
(
o
->
in1
,
regs
[(
r1
+
1
)
&
15
]);
}
static
void
in1_r2
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
static
void
in1_r2
(
DisasContext
*
s
,
DisasFields
*
f
,
DisasOps
*
o
)
{
{
o
->
in1
=
load_reg
(
get_field
(
f
,
r2
));
o
->
in1
=
load_reg
(
get_field
(
f
,
r2
));
...
...
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