提交 cef3017c 编写于 作者: A aliguori

Clean some PCI defines (Stefan Weil)

this patch adds some more defines from linux/pci_regs.h to
hw/pci.h. There is now no longer a need to define them in
eepro100.c, so they were removed there.

Some defines from linux/pci_regs.h had similar, but not
the same defines in hw/pci.h (PCI_REVISION_ID / PCI_REVISION,
PCI_SUBSYSTEM_VENDOR_ID / PCI_SUBVENDOR_ID,
PCI_SUBSYSTEM_ID / PCI_SUBDEVICE_ID).

I suggest to use the "standard" from linux/pci_regs.h and
replace the "old" Qemu ones. To facilitate the migration,
my patch does not remove the old defines but marks them
as obsolete. After a migration to the "standard" defines,
pci.h could use linux/pci_regs.h which is far more complete.

The patch is needed for an updated maintainer version of
hw/eepro100.c which I'd like to see in Qemu stable.

 * Remove declarations already declared in header file from eepro100.c
 * Add missing declarations from pci_regs.h to pci.h
 * Mark "non-standard" declarations in pci.h as obsolete
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6901 c046a42c-6fe2-441c-8c8c-71466251a162
上级 81f099ad
......@@ -47,12 +47,6 @@
/* Common declarations for all PCI devices. */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_REVISION_ID 0x08 /* 8 bits */
#define PCI_CONFIG_8(offset, value) \
(pci_conf[offset] = (value))
#define PCI_CONFIG_16(offset, value) \
......
......@@ -55,7 +55,7 @@ extern target_phys_addr_t pci_mem_base;
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
#define PCI_VENDOR_ID_INTEL 0x8086
/* Intel (0x8086) */
#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
......@@ -92,20 +92,27 @@ typedef struct PCIIORegion {
#define PCI_DEVICES_MAX 64
/* Declarations from linux/pci_regs.h */
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_REVISION 0x08
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_REVISION_ID 0x08 /* 8 bits */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
#define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
/* Bits in the PCI Status Register (PCI 2.3 spec) */
#define PCI_STATUS_RESERVED1 0x007
#define PCI_STATUS_INT_STATUS 0x008
......
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