Fix MIPS64 R2 instructions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3686 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/op.c

@@ -683,8 +683,8 @@ void op_drotr (void)
     target_ulong tmp;
 
     if (T1) {
-       tmp = T0 << (0x40 - T1);
-       T0 = (T0 >> T1) | tmp;
+        tmp = T0 << (0x40 - T1);
+        T0 = (T0 >> T1) | tmp;
     }
     FORCE_RET();
 }
@@ -693,10 +693,8 @@ void op_drotr32 (void)
 {
     target_ulong tmp;
 
-    if (T1) {
-       tmp = T0 << (0x40 - (32 + T1));
-       T0 = (T0 >> (32 + T1)) | tmp;
-    }
+    tmp = T0 << (0x40 - (32 + T1));
+    T0 = (T0 >> (32 + T1)) | tmp;
     FORCE_RET();
 }
 
@@ -724,10 +722,10 @@ void op_drotrv (void)
 
     T0 &= 0x3F;
     if (T0) {
-       tmp = T1 << (0x40 - T0);
-       T0 = (T1 >> T0) | tmp;
+        tmp = T1 << (0x40 - T0);
+        T0 = (T1 >> T0) | tmp;
     } else
-       T0 = T1;
+        T0 = T1;
     FORCE_RET();
 }
 
@@ -3091,7 +3089,7 @@ void op_ext(void)
     unsigned int pos = PARAM1;
     unsigned int size = PARAM2;
 
-    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
+    T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
     FORCE_RET();
 }
 
@@ -3101,13 +3099,13 @@ void op_ins(void)
     unsigned int size = PARAM2;
     target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
 
-    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
+    T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask));
     FORCE_RET();
 }
 
 void op_wsbh(void)
 {
-    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
+    T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF));
     FORCE_RET();
 }
 
@@ -3117,7 +3115,7 @@ void op_dext(void)
     unsigned int pos = PARAM1;
     unsigned int size = PARAM2;
 
-    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
+    T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
     FORCE_RET();
 }
 
@@ -3125,7 +3123,7 @@ void op_dins(void)
 {
     unsigned int pos = PARAM1;
     unsigned int size = PARAM2;
-    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
+    target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
 
     T0 = (T0 & ~mask) | ((T1 << pos) & mask);
     FORCE_RET();
@@ -3139,7 +3137,8 @@ void op_dsbh(void)
 
 void op_dshd(void)
 {
-    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
+    T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
+    T0 = (T1 << 32) | (T1 >> 32);
     FORCE_RET();
 }
 #endif

target-mips/op_helper.c

@@ -106,8 +106,8 @@ void do_drotr (void)
     target_ulong tmp;
 
     if (T1) {
-       tmp = T0 << (0x40 - T1);
-       T0 = (T0 >> T1) | tmp;
+        tmp = T0 << (0x40 - T1);
+        T0 = (T0 >> T1) | tmp;
     }
 }
 
@@ -115,10 +115,8 @@ void do_drotr32 (void)
 {
     target_ulong tmp;
 
-    if (T1) {
-       tmp = T0 << (0x40 - (32 + T1));
-       T0 = (T0 >> (32 + T1)) | tmp;
-    }
+    tmp = T0 << (0x40 - (32 + T1));
+    T0 = (T0 >> (32 + T1)) | tmp;
 }
 
 void do_dsllv (void)
@@ -142,10 +140,10 @@ void do_drotrv (void)
 
     T0 &= 0x3F;
     if (T0) {
-       tmp = T1 << (0x40 - T0);
-       T0 = (T1 >> T0) | tmp;
+        tmp = T1 << (0x40 - T0);
+        T0 = (T1 >> T0) | tmp;
     } else
-       T0 = T1;
+        T0 = T1;
 }
 
 void do_dclo (void)

target-mips/translate.c

@@ -1897,43 +1897,49 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
             goto fail;
         gen_op_ext(lsb, msb + 1);
         break;
+#if defined(TARGET_MIPS64)
     case OPC_DEXTM:
         if (lsb + msb > 63)
             goto fail;
-        gen_op_ext(lsb, msb + 1 + 32);
+        gen_op_dext(lsb, msb + 1 + 32);
         break;
     case OPC_DEXTU:
         if (lsb + msb > 63)
             goto fail;
-        gen_op_ext(lsb + 32, msb + 1);
+        gen_op_dext(lsb + 32, msb + 1);
         break;
     case OPC_DEXT:
-        gen_op_ext(lsb, msb + 1);
+        if (lsb + msb > 63)
+            goto fail;
+        gen_op_dext(lsb, msb + 1);
         break;
+#endif
     case OPC_INS:
         if (lsb > msb)
             goto fail;
         GEN_LOAD_REG_TN(T0, rt);
         gen_op_ins(lsb, msb - lsb + 1);
         break;
+#if defined(TARGET_MIPS64)
     case OPC_DINSM:
         if (lsb > msb)
             goto fail;
         GEN_LOAD_REG_TN(T0, rt);
-        gen_op_ins(lsb, msb - lsb + 1 + 32);
+        gen_op_dins(lsb, msb - lsb + 1 + 32);
         break;
     case OPC_DINSU:
         if (lsb > msb)
             goto fail;
         GEN_LOAD_REG_TN(T0, rt);
-        gen_op_ins(lsb + 32, msb - lsb + 1);
+        gen_op_dins(lsb + 32, msb - lsb + 1);
         break;
     case OPC_DINS:
         if (lsb > msb)
             goto fail;
         GEN_LOAD_REG_TN(T0, rt);
-        gen_op_ins(lsb, msb - lsb + 1);
+        gen_op_dins(lsb, msb - lsb + 1);
         break;
+#endif
     default:
 fail:
         MIPS_INVAL("bitops");
@@ -6156,6 +6162,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
                 break;
             }
             GEN_STORE_TN_REG(rd, T0);
+            break;
 #endif
         default:            /* Invalid */
             MIPS_INVAL("special3");