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提交 b42ec42d 编写于 作者: A aurel32
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DB-DMA cleanup 

Signed-off-by: NLaurent Vivier <Laurent@vivier.eu>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6676 c046a42c-6fe2-441c-8c8c-71466251a162
上级 927e3a4e
隐藏空白更改
内联 并排
Showing with 133 addition and 164 deletion
hw/ide.c
浏览文件 @ b42ec42d
...@@ -3429,71 +3429,69 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, ...@@ -3429,71 +3429,69 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
typedef struct MACIOIDEState { typedef struct MACIOIDEState {
IDEState ide_if[2]; IDEState ide_if[2];
void *dbdma;
int stream_index; int stream_index;
} MACIOIDEState; } MACIOIDEState;
static int pmac_atapi_read(DBDMA_transfer *info, DBDMA_transfer_cb cb) static void pmac_atapi_read(DBDMA_io *io)
{ {
MACIOIDEState *m = info->opaque; MACIOIDEState *m = io->opaque;
IDEState *s = m->ide_if->cur_drive; IDEState *s = m->ide_if->cur_drive;
int ret; int ret, len;
if (s->lba == -1)
return 0;
info->buf_pos = 0;
while (info->buf_pos < info->len && s->packet_transfer_size > 0) { while (io->len > 0 &&
s->packet_transfer_size > 0) {
ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size); len = s->cd_sector_size;
ret = cd_read_sector(s->bs, s->lba, s->io_buffer, len);
if (ret < 0) { if (ret < 0) {
io->dma_end(io);
ide_transfer_stop(s); ide_transfer_stop(s);
ide_atapi_io_error(s, ret); ide_atapi_io_error(s, ret);
return info->buf_pos; return;
} }
info->buf = s->io_buffer + m->stream_index; if (len > io->len)
len = io->len;
info->buf_len = s->cd_sector_size;
if (info->buf_pos + info->buf_len > info->len)
info->buf_len = info->len - info->buf_pos;
cb(info); cpu_physical_memory_write(io->addr,
s->io_buffer + m->stream_index, len);
/* db-dma can ask for 512 bytes whereas block size is 2048... */ /* db-dma can ask for 512 bytes whereas block size is 2048... */
m->stream_index += info->buf_len; m->stream_index += len;
s->lba += m->stream_index / s->cd_sector_size; s->lba += m->stream_index / s->cd_sector_size;
m->stream_index %= s->cd_sector_size; m->stream_index %= s->cd_sector_size;
info->buf_pos += info->buf_len; io->len -= len;
s->packet_transfer_size -= info->buf_len; io->addr += len;
s->packet_transfer_size -= len;
} }
if (io->len <= 0)
io->dma_end(io);
if (s->packet_transfer_size <= 0) { if (s->packet_transfer_size <= 0) {
s->status = READY_STAT | SEEK_STAT; s->status = READY_STAT | SEEK_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO
| ATAPI_INT_REASON_CD; | ATAPI_INT_REASON_CD;
ide_set_irq(s); ide_set_irq(s);
} }
return info->buf_pos;
} }
static int pmac_ide_transfer(DBDMA_transfer *info, static void pmac_ide_transfer(DBDMA_io *io)
DBDMA_transfer_cb cb)
{ {
MACIOIDEState *m = info->opaque; MACIOIDEState *m = io->opaque;
IDEState *s = m->ide_if->cur_drive; IDEState *s = m->ide_if->cur_drive;
int64_t sector_num; int64_t sector_num;
int ret, n; int ret, n;
int len;
if (s->is_cdrom) if (s->is_cdrom) {
return pmac_atapi_read(info, cb); pmac_atapi_read(io);
return;
}
info->buf = s->io_buffer; while (io->len > 0 && s->nsector > 0) {
info->buf_pos = 0;
while (info->buf_pos < info->len && s->nsector > 0) {
sector_num = ide_get_sector(s); sector_num = ide_get_sector(s);
...@@ -3501,36 +3499,40 @@ static int pmac_ide_transfer(DBDMA_transfer *info, ...@@ -3501,36 +3499,40 @@ static int pmac_ide_transfer(DBDMA_transfer *info,
if (n > IDE_DMA_BUF_SECTORS) if (n > IDE_DMA_BUF_SECTORS)
n = IDE_DMA_BUF_SECTORS; n = IDE_DMA_BUF_SECTORS;
info->buf_len = n << 9; len = n << 9;
if (info->buf_pos + info->buf_len > info->len) if (len > io->len)
info->buf_len = info->len - info->buf_pos; len = io->len;
n = info->buf_len >> 9; n = (len + 511) >> 9;
if (s->is_read) { if (s->is_read) {
ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
if (ret == 0) cpu_physical_memory_write(io->addr, s->io_buffer, len);
cb(info);
} else { } else {
cb(info); cpu_physical_memory_read(io->addr, s->io_buffer, len);
ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
} }
if (ret != 0) { if (ret != 0) {
io->dma_end(io);
ide_rw_error(s); ide_rw_error(s);
return info->buf_pos; return;
} }
info->buf_pos += n << 9; io->len -= len;
io->addr += len;
ide_set_sector(s, sector_num + n); ide_set_sector(s, sector_num + n);
s->nsector -= n; s->nsector -= n;
} }
if (io->len <= 0)
io->dma_end(io);
if (s->nsector <= 0) { if (s->nsector <= 0) {
s->status = READY_STAT | SEEK_STAT; s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s); ide_set_irq(s);
} }
return info->buf_pos; return;
} }
/* PowerMac IDE memory IO */ /* PowerMac IDE memory IO */
...@@ -3709,10 +3711,8 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq, ...@@ -3709,10 +3711,8 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
d = qemu_mallocz(sizeof(MACIOIDEState)); d = qemu_mallocz(sizeof(MACIOIDEState));
ide_init2(d->ide_if, hd_table[0], hd_table[1], irq); ide_init2(d->ide_if, hd_table[0], hd_table[1], irq);
if (dbdma) { if (dbdma)
d->dbdma = dbdma;
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, d); DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, d);
}
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read, pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, d); pmac_ide_write, d);
......
hw/mac_dbdma.c
浏览文件 @ b42ec42d
...@@ -158,9 +158,10 @@ typedef struct DBDMA_channel { ...@@ -158,9 +158,10 @@ typedef struct DBDMA_channel {
int channel; int channel;
uint32_t regs[DBDMA_REGS]; uint32_t regs[DBDMA_REGS];
qemu_irq irq; qemu_irq irq;
DBDMA_transfer io; DBDMA_io io;
DBDMA_transfer_handler transfer_handler; DBDMA_rw rw;
dbdma_cmd current; dbdma_cmd current;
int processing;
} DBDMA_channel; } DBDMA_channel;
#ifdef DEBUG_DBDMA #ifdef DEBUG_DBDMA
...@@ -218,7 +219,7 @@ static void conditional_interrupt(DBDMA_channel *ch) ...@@ -218,7 +219,7 @@ static void conditional_interrupt(DBDMA_channel *ch)
DBDMA_DPRINTF("conditional_interrupt\n"); DBDMA_DPRINTF("conditional_interrupt\n");
intr = be16_to_cpu(current->command) & INTR_MASK; intr = le16_to_cpu(current->command) & INTR_MASK;
switch(intr) { switch(intr) {
case INTR_NEVER: /* don't interrupt */ case INTR_NEVER: /* don't interrupt */
...@@ -257,7 +258,7 @@ static int conditional_wait(DBDMA_channel *ch) ...@@ -257,7 +258,7 @@ static int conditional_wait(DBDMA_channel *ch)
DBDMA_DPRINTF("conditional_wait\n"); DBDMA_DPRINTF("conditional_wait\n");
wait = be16_to_cpu(current->command) & WAIT_MASK; wait = le16_to_cpu(current->command) & WAIT_MASK;
switch(wait) { switch(wait) {
case WAIT_NEVER: /* don't wait */ case WAIT_NEVER: /* don't wait */
...@@ -318,7 +319,7 @@ static void conditional_branch(DBDMA_channel *ch) ...@@ -318,7 +319,7 @@ static void conditional_branch(DBDMA_channel *ch)
/* check if we must branch */ /* check if we must branch */
br = be16_to_cpu(current->command) & BR_MASK; br = le16_to_cpu(current->command) & BR_MASK;
switch(br) { switch(br) {
case BR_NEVER: /* don't branch */ case BR_NEVER: /* don't branch */
...@@ -352,38 +353,35 @@ static void conditional_branch(DBDMA_channel *ch) ...@@ -352,38 +353,35 @@ static void conditional_branch(DBDMA_channel *ch)
} }
} }
static int dbdma_read_memory(DBDMA_transfer *io) static QEMUBH *dbdma_bh;
{ static void channel_run(DBDMA_channel *ch);
DBDMA_channel *ch = io->channel;
dbdma_cmd *current = &ch->current;
DBDMA_DPRINTF("DBDMA_read_memory\n");
cpu_physical_memory_read(le32_to_cpu(current->phy_addr) + io->buf_pos,
io->buf, io->buf_len);
return io->buf_len;
}
static int dbdma_write_memory(DBDMA_transfer *io) static void dbdma_end(DBDMA_io *io)
{ {
DBDMA_channel *ch = io->channel; DBDMA_channel *ch = io->channel;
dbdma_cmd *current = &ch->current; dbdma_cmd *current = &ch->current;
DBDMA_DPRINTF("DBDMA_write_memory\n"); if (conditional_wait(ch))
goto wait;
cpu_physical_memory_write(le32_to_cpu(current->phy_addr) + io->buf_pos, current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
io->buf, io->buf_len); current->res_count = cpu_to_le16(be32_to_cpu(io->len));
dbdma_cmdptr_save(ch);
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
conditional_interrupt(ch);
conditional_branch(ch);
return io->buf_len; wait:
ch->processing = 0;
if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
(ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE)))
channel_run(ch);
} }
static int start_output(DBDMA_channel *ch, int key, uint32_t addr, static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t req_count, int is_last) uint16_t req_count, int is_last)
{ {
dbdma_cmd *current = &ch->current;
uint32_t n;
DBDMA_DPRINTF("start_output\n"); DBDMA_DPRINTF("start_output\n");
/* KEY_REGS, KEY_DEVICE and KEY_STREAM /* KEY_REGS, KEY_DEVICE and KEY_STREAM
...@@ -393,35 +391,21 @@ static int start_output(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -393,35 +391,21 @@ static int start_output(DBDMA_channel *ch, int key, uint32_t addr,
DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key); DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
if (!addr || key > KEY_STREAM3) { if (!addr || key > KEY_STREAM3) {
kill_channel(ch); kill_channel(ch);
return 0; return;
} }
ch->io.buf = NULL; ch->io.addr = addr;
ch->io.buf_pos = 0;
ch->io.buf_len = 0;
ch->io.len = req_count; ch->io.len = req_count;
ch->io.is_last = is_last; ch->io.is_last = is_last;
n = ch->transfer_handler(&ch->io, dbdma_read_memory); ch->io.dma_end = dbdma_end;
ch->io.is_dma_out = 1;
if (conditional_wait(ch)) ch->processing = 1;
return 1; ch->rw(&ch->io);
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
current->res_count = cpu_to_le16(0);
dbdma_cmdptr_save(ch);
conditional_interrupt(ch);
conditional_branch(ch);
return 1;
} }
static int start_input(DBDMA_channel *ch, int key, uint32_t addr, static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t req_count, int is_last) uint16_t req_count, int is_last)
{ {
dbdma_cmd *current = &ch->current;
uint32_t n;
DBDMA_DPRINTF("start_input\n"); DBDMA_DPRINTF("start_input\n");
/* KEY_REGS, KEY_DEVICE and KEY_STREAM /* KEY_REGS, KEY_DEVICE and KEY_STREAM
...@@ -430,30 +414,19 @@ static int start_input(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -430,30 +414,19 @@ static int start_input(DBDMA_channel *ch, int key, uint32_t addr,
if (!addr || key > KEY_STREAM3) { if (!addr || key > KEY_STREAM3) {
kill_channel(ch); kill_channel(ch);
return 0; return;
} }
ch->io.buf = NULL; ch->io.addr = addr;
ch->io.buf_pos = 0;
ch->io.buf_len = 0;
ch->io.len = req_count; ch->io.len = req_count;
ch->io.is_last = is_last; ch->io.is_last = is_last;
n = ch->transfer_handler(&ch->io, dbdma_write_memory); ch->io.dma_end = dbdma_end;
ch->io.is_dma_out = 0;
if (conditional_wait(ch)) ch->processing = 1;
return 1; ch->rw(&ch->io);
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
current->res_count = cpu_to_le16(0);
dbdma_cmdptr_save(ch);
conditional_interrupt(ch);
conditional_branch(ch);
return 1;
} }
static int load_word(DBDMA_channel *ch, int key, uint32_t addr, static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t len) uint16_t len)
{ {
dbdma_cmd *current = &ch->current; dbdma_cmd *current = &ch->current;
...@@ -466,7 +439,7 @@ static int load_word(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -466,7 +439,7 @@ static int load_word(DBDMA_channel *ch, int key, uint32_t addr,
if (key != KEY_SYSTEM) { if (key != KEY_SYSTEM) {
printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key); printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
kill_channel(ch); kill_channel(ch);
return 0; return;
} }
cpu_physical_memory_read(addr, (uint8_t*)&val, len); cpu_physical_memory_read(addr, (uint8_t*)&val, len);
...@@ -479,18 +452,20 @@ static int load_word(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -479,18 +452,20 @@ static int load_word(DBDMA_channel *ch, int key, uint32_t addr,
current->cmd_dep = val; current->cmd_dep = val;
if (conditional_wait(ch)) if (conditional_wait(ch))
return 1; goto wait;
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
dbdma_cmdptr_save(ch); dbdma_cmdptr_save(ch);
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
conditional_interrupt(ch); conditional_interrupt(ch);
next(ch); next(ch);
return 1; wait:
qemu_bh_schedule(dbdma_bh);
} }
static int store_word(DBDMA_channel *ch, int key, uint32_t addr, static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t len) uint16_t len)
{ {
dbdma_cmd *current = &ch->current; dbdma_cmd *current = &ch->current;
...@@ -503,7 +478,7 @@ static int store_word(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -503,7 +478,7 @@ static int store_word(DBDMA_channel *ch, int key, uint32_t addr,
if (key != KEY_SYSTEM) { if (key != KEY_SYSTEM) {
printf("DBDMA: STORE_WORD, unimplemented key %x\n", key); printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
kill_channel(ch); kill_channel(ch);
return 0; return;
} }
val = current->cmd_dep; val = current->cmd_dep;
...@@ -515,23 +490,25 @@ static int store_word(DBDMA_channel *ch, int key, uint32_t addr, ...@@ -515,23 +490,25 @@ static int store_word(DBDMA_channel *ch, int key, uint32_t addr,
cpu_physical_memory_write(addr, (uint8_t*)&val, len); cpu_physical_memory_write(addr, (uint8_t*)&val, len);
if (conditional_wait(ch)) if (conditional_wait(ch))
return 1; goto wait;
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
dbdma_cmdptr_save(ch); dbdma_cmdptr_save(ch);
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
conditional_interrupt(ch); conditional_interrupt(ch);
next(ch); next(ch);
return 1; wait:
qemu_bh_schedule(dbdma_bh);
} }
static int nop(DBDMA_channel *ch) static void nop(DBDMA_channel *ch)
{ {
dbdma_cmd *current = &ch->current; dbdma_cmd *current = &ch->current;
if (conditional_wait(ch)) if (conditional_wait(ch))
return 1; goto wait;
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
dbdma_cmdptr_save(ch); dbdma_cmdptr_save(ch);
...@@ -539,19 +516,18 @@ static int nop(DBDMA_channel *ch) ...@@ -539,19 +516,18 @@ static int nop(DBDMA_channel *ch)
conditional_interrupt(ch); conditional_interrupt(ch);
conditional_branch(ch); conditional_branch(ch);
return 1; wait:
qemu_bh_schedule(dbdma_bh);
} }
static int stop(DBDMA_channel *ch) static void stop(DBDMA_channel *ch)
{ {
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD)); ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH));
/* the stop command does not increment command pointer */ /* the stop command does not increment command pointer */
return 0;
} }
static int channel_run(DBDMA_channel *ch) static void channel_run(DBDMA_channel *ch)
{ {
dbdma_cmd *current = &ch->current; dbdma_cmd *current = &ch->current;
uint16_t cmd, key; uint16_t cmd, key;
...@@ -569,10 +545,12 @@ static int channel_run(DBDMA_channel *ch) ...@@ -569,10 +545,12 @@ static int channel_run(DBDMA_channel *ch)
switch (cmd) { switch (cmd) {
case DBDMA_NOP: case DBDMA_NOP:
return nop(ch); nop(ch);
return;
case DBDMA_STOP: case DBDMA_STOP:
return stop(ch); stop(ch);
return;
} }
key = le16_to_cpu(current->command) & 0x0700; key = le16_to_cpu(current->command) & 0x0700;
...@@ -582,21 +560,25 @@ static int channel_run(DBDMA_channel *ch) ...@@ -582,21 +560,25 @@ static int channel_run(DBDMA_channel *ch)
if (key == KEY_STREAM4) { if (key == KEY_STREAM4) {
printf("command %x, invalid key 4\n", cmd); printf("command %x, invalid key 4\n", cmd);
kill_channel(ch); kill_channel(ch);
return 0; return;
} }
switch (cmd) { switch (cmd) {
case OUTPUT_MORE: case OUTPUT_MORE:
return start_output(ch, key, phy_addr, req_count, 0); start_output(ch, key, phy_addr, req_count, 0);
return;
case OUTPUT_LAST: case OUTPUT_LAST:
return start_output(ch, key, phy_addr, req_count, 1); start_output(ch, key, phy_addr, req_count, 1);
return;
case INPUT_MORE: case INPUT_MORE:
return start_input(ch, key, phy_addr, req_count, 0); start_input(ch, key, phy_addr, req_count, 0);
return;
case INPUT_LAST: case INPUT_LAST:
return start_input(ch, key, phy_addr, req_count, 1); start_input(ch, key, phy_addr, req_count, 1);
return;
} }
if (key < KEY_REGS) { if (key < KEY_REGS) {
...@@ -620,35 +602,24 @@ static int channel_run(DBDMA_channel *ch) ...@@ -620,35 +602,24 @@ static int channel_run(DBDMA_channel *ch)
switch (cmd) { switch (cmd) {
case LOAD_WORD: case LOAD_WORD:
return load_word(ch, key, phy_addr, req_count); load_word(ch, key, phy_addr, req_count);
return;
case STORE_WORD: case STORE_WORD:
return store_word(ch, key, phy_addr, req_count); store_word(ch, key, phy_addr, req_count);
return;
} }
return 0;
} }
static QEMUBH *dbdma_bh;
static void DBDMA_run (DBDMA_channel *ch) static void DBDMA_run (DBDMA_channel *ch)
{ {
int channel; int channel;
int rearm = 0;
for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) { for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]); uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
if ((status & RUN) && (status & ACTIVE)) { if (!ch->processing && (status & RUN) && (status & ACTIVE))
if (status & FLUSH) channel_run(ch);
while (channel_run(ch));
else if (channel_run(ch))
rearm = 1;
}
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
} }
if (rearm)
qemu_bh_schedule_idle(dbdma_bh);
} }
static void DBDMA_run_bh(void *opaque) static void DBDMA_run_bh(void *opaque)
...@@ -661,7 +632,7 @@ static void DBDMA_run_bh(void *opaque) ...@@ -661,7 +632,7 @@ static void DBDMA_run_bh(void *opaque)
} }
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_transfer_handler transfer_handler, DBDMA_rw rw,
void *opaque) void *opaque)
{ {
DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan; DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
...@@ -670,7 +641,7 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, ...@@ -670,7 +641,7 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
ch->irq = irq; ch->irq = irq;
ch->channel = nchan; ch->channel = nchan;
ch->transfer_handler = transfer_handler; ch->rw = rw;
ch->io.opaque = opaque; ch->io.opaque = opaque;
ch->io.channel = ch; ch->io.channel = ch;
} }
...@@ -714,11 +685,8 @@ dbdma_control_write(DBDMA_channel *ch) ...@@ -714,11 +685,8 @@ dbdma_control_write(DBDMA_channel *ch)
ch->regs[DBDMA_STATUS] = cpu_to_be32(status); ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
if (status & ACTIVE) { if (status & ACTIVE)
qemu_bh_schedule_idle(dbdma_bh); qemu_bh_schedule(dbdma_bh);
if (status & FLUSH)
DBDMA_schedule();
}
} }
static void dbdma_writel (void *opaque, static void dbdma_writel (void *opaque,
......
hw/mac_dbdma.h
浏览文件 @ b42ec42d
...@@ -20,22 +20,23 @@ ...@@ -20,22 +20,23 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
typedef struct { typedef struct DBDMA_io DBDMA_io;
typedef void (*DBDMA_rw)(DBDMA_io *io);
typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
void *opaque; void *opaque;
void *channel; void *channel;
target_phys_addr_t addr;
int len; int len;
int is_last; int is_last;
void *buf; int is_dma_out;
int buf_pos; DBDMA_end dma_end;
int buf_len; };
} DBDMA_transfer;
typedef int (*DBDMA_transfer_cb)(DBDMA_transfer *info);
typedef int (*DBDMA_transfer_handler)(DBDMA_transfer *info,
DBDMA_transfer_cb cb);
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_transfer_handler transfer_handler, DBDMA_rw rw,
void *opaque); void *opaque);
void DBDMA_schedule(void); void DBDMA_schedule(void);
void* DBDMA_init (int *dbdma_mem_index); void* DBDMA_init (int *dbdma_mem_index);
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