aspeed_sdmc: Set 'cache initial sequence' always true
The SDRAM training routine sets the 'Enable cache initial' bit, and then waits for the 'cache initial sequence' to be done. Have it always return done, as there is no other side effects that the model needs to implement. This allows the upstream u-boot training to proceed on the ast2500-evb board. Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NCédric Le Goater <clg@kaod.org> Tested-by: NCédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-4-joel@jms.id.au Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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