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提交 a3ce3668 编写于 作者: B Blue Swirl
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Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm 

* 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access
  target-arm: Minimal implementation of performance counters
  Revert "Makefile.target: Allow target helpers to be in any *_helper.c file"
  Revert "target-arm: Use global env in neon_helper.c helpers"
  target-arm: Pass fp status pointer explicitly to neon fp helpers
  target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
  target-arm: Add helper function to generate code to get fpstatus pointer
  Revert "target-arm: Use global env in iwmmxt_helper.c helpers"

Conflicts:
	Makefile.target
上级 03ff0958 82845826
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Showing with 753 addition and 493 deletion
Makefile.target
浏览文件 @ a3ce3668
......@@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h
# HELPER_CFLAGS is used for all the code compiled with static register
# variables
%_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
# Note: this is a workaround. The real fix is to avoid compiling
# cpu_signal_handler() in user-exec.c.
......
target-arm/cpu.h
浏览文件 @ a3ce3668
......@@ -133,6 +133,12 @@ typedef struct CPUARMState {
uint32_t c7_par; /* Translation result. */
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint32_t c9_pmcr; /* performance monitor control register */
uint32_t c9_pmcnten; /* perf monitor counter enables */
uint32_t c9_pmovsr; /* perf monitor overflow status */
uint32_t c9_pmxevtyper; /* perf monitor event type */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint32_t c13_fcse; /* FCSE PID. */
uint32_t c13_context; /* Context ID. */
uint32_t c13_tls1; /* User RW Thread register. */
......@@ -438,7 +444,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
#define CPU_SAVE_VERSION 3
#define CPU_SAVE_VERSION 4
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
......
target-arm/helper.c
浏览文件 @ a3ce3668
......@@ -269,6 +269,10 @@ void cpu_reset(CPUARMState *env)
}
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
env->cp15.c2_base_mask = 0xffffc000u;
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement no event counters.
*/
env->cp15.c9_pmcr = (id & 0xff000000);
#endif
set_flush_to_zero(1, &env->vfp.standard_fp_status);
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
......@@ -1587,6 +1591,81 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
case 1: /* TCM memory region registers. */
/* Not implemented. */
goto bad_reg;
case 12: /* Performance monitor control */
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
* follow (although we don't actually implement any counters)
*/
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
}
switch (op2) {
case 0: /* performance monitor control register */
/* only the DP, X, D and E bits are writable */
env->cp15.c9_pmcr &= ~0x39;
env->cp15.c9_pmcr |= (val & 0x39);
break;
case 1: /* Count enable set register */
val &= (1 << 31);
env->cp15.c9_pmcnten |= val;
break;
case 2: /* Count enable clear */
val &= (1 << 31);
env->cp15.c9_pmcnten &= ~val;
break;
case 3: /* Overflow flag status */
env->cp15.c9_pmovsr &= ~val;
break;
case 4: /* Software increment */
/* RAZ/WI since we don't implement the software-count event */
break;
case 5: /* Event counter selection register */
/* Since we don't implement any events, writing to this register
* is actually UNPREDICTABLE. So we choose to RAZ/WI.
*/
break;
default:
goto bad_reg;
}
break;
case 13: /* Performance counters */
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
}
switch (op2) {
case 0: /* Cycle count register: not implemented, so RAZ/WI */
break;
case 1: /* Event type select */
env->cp15.c9_pmxevtyper = val & 0xff;
break;
case 2: /* Event count register */
/* Unimplemented (we have no events), RAZ/WI */
break;
default:
goto bad_reg;
}
break;
case 14: /* Performance monitor control */
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
}
switch (op2) {
case 0: /* user enable */
env->cp15.c9_pmuserenr = val & 1;
/* changes access rights for cp registers, so flush tbs */
tb_flush(env);
break;
case 1: /* interrupt enable set */
/* We have no event counters so only the C bit can be changed */
val &= (1 << 31);
env->cp15.c9_pminten |= val;
break;
case 2: /* interrupt enable clear */
val &= (1 << 31);
env->cp15.c9_pminten &= ~val;
break;
}
break;
default:
goto bad_reg;
}
......@@ -1878,27 +1957,81 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
return 0;
case 8: /* MMU TLB control. */
goto bad_reg;
case 9: /* Cache lockdown. */
switch (op1) {
case 0: /* L1 cache. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
return 0;
case 9:
switch (crm) {
case 0: /* Cache lockdown */
switch (op1) {
case 0: /* L1 cache. */
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
return 0;
}
switch (op2) {
case 0:
return env->cp15.c9_data;
case 1:
return env->cp15.c9_insn;
default:
goto bad_reg;
}
case 1: /* L2 cache */
if (crm != 0) {
goto bad_reg;
}
/* L2 Lockdown and Auxiliary control. */
return 0;
default:
goto bad_reg;
}
break;
case 12: /* Performance monitor control */
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
}
switch (op2) {
case 0:
return env->cp15.c9_data;
case 1:
return env->cp15.c9_insn;
case 0: /* performance monitor control register */
return env->cp15.c9_pmcr;
case 1: /* count enable set */
case 2: /* count enable clear */
return env->cp15.c9_pmcnten;
case 3: /* overflow flag status */
return env->cp15.c9_pmovsr;
case 4: /* software increment */
case 5: /* event counter selection register */
return 0; /* Unimplemented, RAZ/WI */
default:
goto bad_reg;
}
case 1: /* L2 cache */
if (crm != 0)
case 13: /* Performance counters */
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
}
switch (op2) {
case 1: /* Event type select */
return env->cp15.c9_pmxevtyper;
case 0: /* Cycle count register */
case 2: /* Event count register */
/* Unimplemented, so RAZ/WI */
return 0;
default:
goto bad_reg;
}
case 14: /* Performance monitor control */
if (!arm_feature(env, ARM_FEATURE_V7)) {
goto bad_reg;
/* L2 Lockdown and Auxiliary control. */
return 0;
}
switch (op2) {
case 0: /* user enable */
return env->cp15.c9_pmuserenr;
case 1: /* interrupt enable set */
case 2: /* interrupt enable clear */
return env->cp15.c9_pminten;
default:
goto bad_reg;
}
default:
goto bad_reg;
}
break;
case 10: /* MMU TLB lockdown. */
/* ??? TLB lockdown not implemented. */
return 0;
......@@ -1994,11 +2127,11 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
case 16: /* PRIMASK */
return (env->uncached_cpsr & CPSR_I) != 0;
case 17: /* FAULTMASK */
return (env->uncached_cpsr & CPSR_F) != 0;
case 18: /* BASEPRI */
case 19: /* BASEPRI_MAX */
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
return env->v7m.basepri;
case 19: /* FAULTMASK */
return (env->uncached_cpsr & CPSR_F) != 0;
case 20: /* CONTROL */
return env->v7m.control;
default:
......@@ -2050,20 +2183,20 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
else
env->uncached_cpsr &= ~CPSR_I;
break;
case 17: /* FAULTMASK */
if (val & 1)
env->uncached_cpsr |= CPSR_F;
else
env->uncached_cpsr &= ~CPSR_F;
break;
case 18: /* BASEPRI */
case 17: /* BASEPRI */
env->v7m.basepri = val & 0xff;
break;
case 19: /* BASEPRI_MAX */
case 18: /* BASEPRI_MAX */
val &= 0xff;
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
env->v7m.basepri = val;
break;
case 19: /* FAULTMASK */
if (val & 1)
env->uncached_cpsr |= CPSR_F;
else
env->uncached_cpsr &= ~CPSR_F;
break;
case 20: /* CONTROL */
env->v7m.control = val & 3;
switch_v7m_sp(env, (val & 2) != 0);
......@@ -2452,13 +2585,15 @@ void vfp_set_fpscr(CPUState *env, uint32_t val)
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
#define VFP_BINOP(name) \
float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
{ \
return float32_ ## name (a, b, &env->vfp.fp_status); \
float_status *fpst = fpstp; \
return float32_ ## name(a, b, fpst); \
} \
float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
{ \
return float64_ ## name (a, b, &env->vfp.fp_status); \
float_status *fpst = fpstp; \
return float64_ ## name(a, b, fpst); \
}
VFP_BINOP(add)
VFP_BINOP(sub)
......
target-arm/helper.h
浏览文件 @ a3ce3668
......@@ -74,14 +74,14 @@ DEF_HELPER_2(set_user_reg, void, i32, i32)
DEF_HELPER_1(vfp_get_fpscr, i32, env)
DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
DEF_HELPER_3(vfp_adds, f32, f32, f32, env)
DEF_HELPER_3(vfp_addd, f64, f64, f64, env)
DEF_HELPER_3(vfp_subs, f32, f32, f32, env)
DEF_HELPER_3(vfp_subd, f64, f64, f64, env)
DEF_HELPER_3(vfp_muls, f32, f32, f32, env)
DEF_HELPER_3(vfp_muld, f64, f64, f64, env)
DEF_HELPER_3(vfp_divs, f32, f32, f32, env)
DEF_HELPER_3(vfp_divd, f64, f64, f64, env)
DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr)
DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr)
DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr)
DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr)
DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr)
DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr)
DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr)
DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr)
DEF_HELPER_1(vfp_negs, f32, f32)
DEF_HELPER_1(vfp_negd, f64, f64)
DEF_HELPER_1(vfp_abss, f32, f32)
......@@ -154,22 +154,22 @@ DEF_HELPER_2(sar_cc, i32, i32, i32)
DEF_HELPER_2(ror_cc, i32, i32, i32)
/* neon_helper.c */
DEF_HELPER_2(neon_qadd_u8, i32, i32, i32)
DEF_HELPER_2(neon_qadd_s8, i32, i32, i32)
DEF_HELPER_2(neon_qadd_u16, i32, i32, i32)
DEF_HELPER_2(neon_qadd_s16, i32, i32, i32)
DEF_HELPER_2(neon_qadd_u32, i32, i32, i32)
DEF_HELPER_2(neon_qadd_s32, i32, i32, i32)
DEF_HELPER_2(neon_qsub_u8, i32, i32, i32)
DEF_HELPER_2(neon_qsub_s8, i32, i32, i32)
DEF_HELPER_2(neon_qsub_u16, i32, i32, i32)
DEF_HELPER_2(neon_qsub_s16, i32, i32, i32)
DEF_HELPER_2(neon_qsub_u32, i32, i32, i32)
DEF_HELPER_2(neon_qsub_s32, i32, i32, i32)
DEF_HELPER_2(neon_qadd_u64, i64, i64, i64)
DEF_HELPER_2(neon_qadd_s64, i64, i64, i64)
DEF_HELPER_2(neon_qsub_u64, i64, i64, i64)
DEF_HELPER_2(neon_qsub_s64, i64, i64, i64)
DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_s8, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_u16, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_u32, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_u32, i32, env, i32, i32)
DEF_HELPER_3(neon_qsub_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qadd_u64, i64, env, i64, i64)
DEF_HELPER_3(neon_qadd_s64, i64, env, i64, i64)
DEF_HELPER_3(neon_qsub_u64, i64, env, i64, i64)
DEF_HELPER_3(neon_qsub_s64, i64, env, i64, i64)
DEF_HELPER_2(neon_hadd_s8, i32, i32, i32)
DEF_HELPER_2(neon_hadd_u8, i32, i32, i32)
......@@ -247,26 +247,26 @@ DEF_HELPER_2(neon_rshl_u32, i32, i32, i32)
DEF_HELPER_2(neon_rshl_s32, i32, i32, i32)
DEF_HELPER_2(neon_rshl_u64, i64, i64, i64)
DEF_HELPER_2(neon_rshl_s64, i64, i64, i64)
DEF_HELPER_2(neon_qshl_u8, i32, i32, i32)
DEF_HELPER_2(neon_qshl_s8, i32, i32, i32)
DEF_HELPER_2(neon_qshl_u16, i32, i32, i32)
DEF_HELPER_2(neon_qshl_s16, i32, i32, i32)
DEF_HELPER_2(neon_qshl_u32, i32, i32, i32)
DEF_HELPER_2(neon_qshl_s32, i32, i32, i32)
DEF_HELPER_2(neon_qshl_u64, i64, i64, i64)
DEF_HELPER_2(neon_qshl_s64, i64, i64, i64)
DEF_HELPER_2(neon_qshlu_s8, i32, i32, i32);
DEF_HELPER_2(neon_qshlu_s16, i32, i32, i32);
DEF_HELPER_2(neon_qshlu_s32, i32, i32, i32);
DEF_HELPER_2(neon_qshlu_s64, i64, i64, i64);
DEF_HELPER_2(neon_qrshl_u8, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_s8, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_u16, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_s16, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_u32, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_s32, i32, i32, i32)
DEF_HELPER_2(neon_qrshl_u64, i64, i64, i64)
DEF_HELPER_2(neon_qrshl_s64, i64, i64, i64)
DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64)
DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64)
DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32);
DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32);
DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32);
DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64);
DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64)
DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
DEF_HELPER_2(neon_add_u8, i32, i32, i32)
DEF_HELPER_2(neon_add_u16, i32, i32, i32)
......@@ -295,22 +295,22 @@ DEF_HELPER_1(neon_cls_s16, i32, i32)
DEF_HELPER_1(neon_cls_s32, i32, i32)
DEF_HELPER_1(neon_cnt_u8, i32, i32)
DEF_HELPER_2(neon_qdmulh_s16, i32, i32, i32)
DEF_HELPER_2(neon_qrdmulh_s16, i32, i32, i32)
DEF_HELPER_2(neon_qdmulh_s32, i32, i32, i32)
DEF_HELPER_2(neon_qrdmulh_s32, i32, i32, i32)
DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32)
DEF_HELPER_1(neon_narrow_u8, i32, i64)
DEF_HELPER_1(neon_narrow_u16, i32, i64)
DEF_HELPER_1(neon_unarrow_sat8, i32, i64)
DEF_HELPER_1(neon_narrow_sat_u8, i32, i64)
DEF_HELPER_1(neon_narrow_sat_s8, i32, i64)
DEF_HELPER_1(neon_unarrow_sat16, i32, i64)
DEF_HELPER_1(neon_narrow_sat_u16, i32, i64)
DEF_HELPER_1(neon_narrow_sat_s16, i32, i64)
DEF_HELPER_1(neon_unarrow_sat32, i32, i64)
DEF_HELPER_1(neon_narrow_sat_u32, i32, i64)
DEF_HELPER_1(neon_narrow_sat_s32, i32, i64)
DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64)
DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64)
DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64)
DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64)
DEF_HELPER_1(neon_narrow_high_u8, i32, i64)
DEF_HELPER_1(neon_narrow_high_u16, i32, i64)
DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64)
......@@ -326,8 +326,8 @@ DEF_HELPER_2(neon_paddl_u16, i64, i64, i64)
DEF_HELPER_2(neon_paddl_u32, i64, i64, i64)
DEF_HELPER_2(neon_subl_u16, i64, i64, i64)
DEF_HELPER_2(neon_subl_u32, i64, i64, i64)
DEF_HELPER_2(neon_addl_saturate_s32, i64, i64, i64)
DEF_HELPER_2(neon_addl_saturate_s64, i64, i64, i64)
DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64)
DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64)
DEF_HELPER_2(neon_abdl_u16, i64, i32, i32)
DEF_HELPER_2(neon_abdl_s16, i64, i32, i32)
DEF_HELPER_2(neon_abdl_u32, i64, i32, i32)
......@@ -343,24 +343,21 @@ DEF_HELPER_1(neon_negl_u16, i64, i64)
DEF_HELPER_1(neon_negl_u32, i64, i64)
DEF_HELPER_1(neon_negl_u64, i64, i64)
DEF_HELPER_1(neon_qabs_s8, i32, i32)
DEF_HELPER_1(neon_qabs_s16, i32, i32)
DEF_HELPER_1(neon_qabs_s32, i32, i32)
DEF_HELPER_1(neon_qneg_s8, i32, i32)
DEF_HELPER_1(neon_qneg_s16, i32, i32)
DEF_HELPER_1(neon_qneg_s32, i32, i32)
DEF_HELPER_2(neon_min_f32, i32, i32, i32)
DEF_HELPER_2(neon_max_f32, i32, i32, i32)
DEF_HELPER_2(neon_abd_f32, i32, i32, i32)
DEF_HELPER_2(neon_add_f32, i32, i32, i32)
DEF_HELPER_2(neon_sub_f32, i32, i32, i32)
DEF_HELPER_2(neon_mul_f32, i32, i32, i32)
DEF_HELPER_2(neon_ceq_f32, i32, i32, i32)
DEF_HELPER_2(neon_cge_f32, i32, i32, i32)
DEF_HELPER_2(neon_cgt_f32, i32, i32, i32)
DEF_HELPER_2(neon_acge_f32, i32, i32, i32)
DEF_HELPER_2(neon_acgt_f32, i32, i32, i32)
DEF_HELPER_2(neon_qabs_s8, i32, env, i32)
DEF_HELPER_2(neon_qabs_s16, i32, env, i32)
DEF_HELPER_2(neon_qabs_s32, i32, env, i32)
DEF_HELPER_2(neon_qneg_s8, i32, env, i32)
DEF_HELPER_2(neon_qneg_s16, i32, env, i32)
DEF_HELPER_2(neon_qneg_s32, i32, env, i32)
DEF_HELPER_3(neon_min_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_max_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr)
/* iwmmxt_helper.c */
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
......@@ -375,47 +372,47 @@ DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64)
DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64)
DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64)
#define DEF_IWMMXT_HELPER_SIZE(name) \
DEF_HELPER_2(iwmmxt_##name##b, i64, i64, i64) \
DEF_HELPER_2(iwmmxt_##name##w, i64, i64, i64) \
DEF_HELPER_2(iwmmxt_##name##l, i64, i64, i64) \
DEF_IWMMXT_HELPER_SIZE(unpackl)
DEF_IWMMXT_HELPER_SIZE(unpackh)
DEF_HELPER_1(iwmmxt_unpacklub, i64, i64)
DEF_HELPER_1(iwmmxt_unpackluw, i64, i64)
DEF_HELPER_1(iwmmxt_unpacklul, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhub, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhuw, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhul, i64, i64)
DEF_HELPER_1(iwmmxt_unpacklsb, i64, i64)
DEF_HELPER_1(iwmmxt_unpacklsw, i64, i64)
DEF_HELPER_1(iwmmxt_unpacklsl, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhsb, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhsw, i64, i64)
DEF_HELPER_1(iwmmxt_unpackhsl, i64, i64)
DEF_IWMMXT_HELPER_SIZE(cmpeq)
DEF_IWMMXT_HELPER_SIZE(cmpgtu)
DEF_IWMMXT_HELPER_SIZE(cmpgts)
DEF_IWMMXT_HELPER_SIZE(mins)
DEF_IWMMXT_HELPER_SIZE(minu)
DEF_IWMMXT_HELPER_SIZE(maxs)
DEF_IWMMXT_HELPER_SIZE(maxu)
DEF_IWMMXT_HELPER_SIZE(subn)
DEF_IWMMXT_HELPER_SIZE(addn)
DEF_IWMMXT_HELPER_SIZE(subu)
DEF_IWMMXT_HELPER_SIZE(addu)
DEF_IWMMXT_HELPER_SIZE(subs)
DEF_IWMMXT_HELPER_SIZE(adds)
DEF_HELPER_2(iwmmxt_avgb0, i64, i64, i64)
DEF_HELPER_2(iwmmxt_avgb1, i64, i64, i64)
DEF_HELPER_2(iwmmxt_avgw0, i64, i64, i64)
DEF_HELPER_2(iwmmxt_avgw1, i64, i64, i64)
#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \
DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \
DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \
DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \
DEF_IWMMXT_HELPER_SIZE_ENV(unpackl)
DEF_IWMMXT_HELPER_SIZE_ENV(unpackh)
DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64)
DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64)
DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq)
DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu)
DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts)
DEF_IWMMXT_HELPER_SIZE_ENV(mins)
DEF_IWMMXT_HELPER_SIZE_ENV(minu)
DEF_IWMMXT_HELPER_SIZE_ENV(maxs)
DEF_IWMMXT_HELPER_SIZE_ENV(maxu)
DEF_IWMMXT_HELPER_SIZE_ENV(subn)
DEF_IWMMXT_HELPER_SIZE_ENV(addn)
DEF_IWMMXT_HELPER_SIZE_ENV(subu)
DEF_IWMMXT_HELPER_SIZE_ENV(addu)
DEF_IWMMXT_HELPER_SIZE_ENV(subs)
DEF_IWMMXT_HELPER_SIZE_ENV(adds)
DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64)
DEF_HELPER_2(iwmmxt_msadb, i64, i64, i64)
......@@ -434,26 +431,26 @@ DEF_HELPER_1(iwmmxt_msbb, i32, i64)
DEF_HELPER_1(iwmmxt_msbw, i32, i64)
DEF_HELPER_1(iwmmxt_msbl, i32, i64)
DEF_HELPER_2(iwmmxt_srlw, i64, i64, i32)
DEF_HELPER_2(iwmmxt_srll, i64, i64, i32)
DEF_HELPER_2(iwmmxt_srlq, i64, i64, i32)
DEF_HELPER_2(iwmmxt_sllw, i64, i64, i32)
DEF_HELPER_2(iwmmxt_slll, i64, i64, i32)
DEF_HELPER_2(iwmmxt_sllq, i64, i64, i32)
DEF_HELPER_2(iwmmxt_sraw, i64, i64, i32)
DEF_HELPER_2(iwmmxt_sral, i64, i64, i32)
DEF_HELPER_2(iwmmxt_sraq, i64, i64, i32)
DEF_HELPER_2(iwmmxt_rorw, i64, i64, i32)
DEF_HELPER_2(iwmmxt_rorl, i64, i64, i32)
DEF_HELPER_2(iwmmxt_rorq, i64, i64, i32)
DEF_HELPER_2(iwmmxt_shufh, i64, i64, i32)
DEF_HELPER_2(iwmmxt_packuw, i64, i64, i64)
DEF_HELPER_2(iwmmxt_packul, i64, i64, i64)
DEF_HELPER_2(iwmmxt_packuq, i64, i64, i64)
DEF_HELPER_2(iwmmxt_packsw, i64, i64, i64)
DEF_HELPER_2(iwmmxt_packsl, i64, i64, i64)
DEF_HELPER_2(iwmmxt_packsq, i64, i64, i64)
DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32)
DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64)
DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32)
DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32)
......@@ -461,15 +458,15 @@ DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32)
DEF_HELPER_2(set_teecr, void, env, i32)
DEF_HELPER_2(neon_unzip8, void, i32, i32)
DEF_HELPER_2(neon_unzip16, void, i32, i32)
DEF_HELPER_2(neon_qunzip8, void, i32, i32)
DEF_HELPER_2(neon_qunzip16, void, i32, i32)
DEF_HELPER_2(neon_qunzip32, void, i32, i32)
DEF_HELPER_2(neon_zip8, void, i32, i32)
DEF_HELPER_2(neon_zip16, void, i32, i32)
DEF_HELPER_2(neon_qzip8, void, i32, i32)
DEF_HELPER_2(neon_qzip16, void, i32, i32)
DEF_HELPER_2(neon_qzip32, void, i32, i32)
DEF_HELPER_3(neon_unzip8, void, env, i32, i32)
DEF_HELPER_3(neon_unzip16, void, env, i32, i32)
DEF_HELPER_3(neon_qunzip8, void, env, i32, i32)
DEF_HELPER_3(neon_qunzip16, void, env, i32, i32)
DEF_HELPER_3(neon_qunzip32, void, env, i32, i32)
DEF_HELPER_3(neon_zip8, void, env, i32, i32)
DEF_HELPER_3(neon_zip16, void, env, i32, i32)
DEF_HELPER_3(neon_qzip8, void, env, i32, i32)
DEF_HELPER_3(neon_qzip16, void, env, i32, i32)
DEF_HELPER_3(neon_qzip32, void, env, i32, i32)
#include "def-helper.h"
target-arm/iwmmxt_helper.c
浏览文件 @ a3ce3668
......@@ -23,7 +23,7 @@
#include <stdio.h>
#include "cpu.h"
#include "exec.h"
#include "exec-all.h"
#include "helper.h"
/* iwMMXt macros extracted from GNU gdb. */
......@@ -162,7 +162,8 @@ uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
(((a >> SH0) & 0xff) << 0) | (((b >> SH0) & 0xff) << 8) | \
......@@ -176,7 +177,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(uint64_t a, uint64_t b) \
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
return a; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
(((a >> SH0) & 0xffff) << 0) | \
......@@ -188,7 +190,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(uint64_t a, uint64_t b) \
NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3); \
return a; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
(((a >> SH0) & 0xffffffff) << 0) | \
......@@ -197,7 +200,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(uint64_t a, uint64_t b) \
NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \
return a; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
uint64_t x) \
{ \
x = \
(((x >> SH0) & 0xff) << 0) | \
......@@ -209,7 +213,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(uint64_t x) \
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
return x; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
uint64_t x) \
{ \
x = \
(((x >> SH0) & 0xffff) << 0) | \
......@@ -218,13 +223,15 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(uint64_t x) \
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
return x; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUState *env, \
uint64_t x) \
{ \
x = (((x >> SH0) & 0xffffffff) << 0); \
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
return x; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
uint64_t x) \
{ \
x = \
((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) | \
......@@ -236,7 +243,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(uint64_t x) \
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
return x; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
uint64_t x) \
{ \
x = \
((uint64_t) EXTEND16((x >> SH0) & 0xffff) << 0) | \
......@@ -245,7 +253,8 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(uint64_t x) \
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
return x; \
} \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(uint64_t x) \
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUState *env, \
uint64_t x) \
{ \
x = EXTEND32((x >> SH0) & 0xffffffff); \
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
......@@ -255,7 +264,8 @@ IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \
......@@ -269,7 +279,8 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(uint64_t a, uint64_t b) \
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
return a; \
} \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \
......@@ -278,7 +289,8 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(uint64_t a, uint64_t b) \
NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); \
return a; \
} \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(uint64_t a, uint64_t b) \
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUState *env, \
uint64_t a, uint64_t b) \
{ \
a = CMP(0, Tl, O, 0xffffffff) | \
CMP(32, Tl, O, 0xffffffff); \
......@@ -317,7 +329,7 @@ IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
#define AVGB(SHR) ((( \
((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
#define IWMMXT_OP_AVGB(r) \
uint64_t HELPER(iwmmxt_avgb##r)(uint64_t a, uint64_t b) \
uint64_t HELPER(iwmmxt_avgb##r)(CPUState *env, uint64_t a, uint64_t b) \
{ \
const int round = r; \
a = AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | \
......@@ -341,7 +353,7 @@ IWMMXT_OP_AVGB(1)
#define AVGW(SHR) ((( \
((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SHR)
#define IWMMXT_OP_AVGW(r) \
uint64_t HELPER(iwmmxt_avgw##r)(uint64_t a, uint64_t b) \
uint64_t HELPER(iwmmxt_avgw##r)(CPUState *env, uint64_t a, uint64_t b) \
{ \
const int round = r; \
a = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); \
......@@ -452,7 +464,7 @@ uint32_t HELPER(iwmmxt_msbl)(uint64_t x)
}
/* FIXME: Split wCASF setting into a separate op to avoid env use. */
uint64_t HELPER(iwmmxt_srlw)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
{
x = (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) |
(((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) |
......@@ -464,7 +476,7 @@ uint64_t HELPER(iwmmxt_srlw)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_srll)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
{
x = ((x & (0xffffffffll << 0)) >> n) |
((x >> n) & (0xffffffffll << 32));
......@@ -473,14 +485,14 @@ uint64_t HELPER(iwmmxt_srll)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_srlq)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_srlq)(CPUState *env, uint64_t x, uint32_t n)
{
x >>= n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
uint64_t HELPER(iwmmxt_sllw)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
{
x = (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) |
(((x & (0xffffll << 16)) << n) & (0xffffll << 16)) |
......@@ -492,7 +504,7 @@ uint64_t HELPER(iwmmxt_sllw)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_slll)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
{
x = ((x << n) & (0xffffffffll << 0)) |
((x & (0xffffffffll << 32)) << n);
......@@ -501,14 +513,14 @@ uint64_t HELPER(iwmmxt_slll)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_sllq)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_sllq)(CPUState *env, uint64_t x, uint32_t n)
{
x <<= n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
uint64_t HELPER(iwmmxt_sraw)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
{
x = ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) |
((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) |
......@@ -520,7 +532,7 @@ uint64_t HELPER(iwmmxt_sraw)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_sral)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
{
x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
(((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
......@@ -529,14 +541,14 @@ uint64_t HELPER(iwmmxt_sral)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_sraq)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_sraq)(CPUState *env, uint64_t x, uint32_t n)
{
x = (int64_t) x >> n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
uint64_t HELPER(iwmmxt_rorw)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
{
x = ((((x & (0xffffll << 0)) >> n) |
((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) |
......@@ -552,7 +564,7 @@ uint64_t HELPER(iwmmxt_rorw)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_rorl)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
{
x = ((x & (0xffffffffll << 0)) >> n) |
((x >> n) & (0xffffffffll << 32)) |
......@@ -563,14 +575,14 @@ uint64_t HELPER(iwmmxt_rorl)(uint64_t x, uint32_t n)
return x;
}
uint64_t HELPER(iwmmxt_rorq)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_rorq)(CPUState *env, uint64_t x, uint32_t n)
{
x = (x >> n) | (x << (64 - n));
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
uint64_t HELPER(iwmmxt_shufh)(uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
{
x = (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) |
(((x >> ((n << 2) & 0x30)) & 0xffff) << 16) |
......@@ -583,7 +595,7 @@ uint64_t HELPER(iwmmxt_shufh)(uint64_t x, uint32_t n)
}
/* TODO: Unsigned-Saturation */
uint64_t HELPER(iwmmxt_packuw)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
......@@ -597,7 +609,7 @@ uint64_t HELPER(iwmmxt_packuw)(uint64_t a, uint64_t b)
return a;
}
uint64_t HELPER(iwmmxt_packul)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
......@@ -607,7 +619,7 @@ uint64_t HELPER(iwmmxt_packul)(uint64_t a, uint64_t b)
return a;
}
uint64_t HELPER(iwmmxt_packuq)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
{
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
......@@ -616,7 +628,7 @@ uint64_t HELPER(iwmmxt_packuq)(uint64_t a, uint64_t b)
}
/* TODO: Signed-Saturation */
uint64_t HELPER(iwmmxt_packsw)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
......@@ -630,7 +642,7 @@ uint64_t HELPER(iwmmxt_packsw)(uint64_t a, uint64_t b)
return a;
}
uint64_t HELPER(iwmmxt_packsl)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
......@@ -640,7 +652,7 @@ uint64_t HELPER(iwmmxt_packsl)(uint64_t a, uint64_t b)
return a;
}
uint64_t HELPER(iwmmxt_packsq)(uint64_t a, uint64_t b)
uint64_t HELPER(iwmmxt_packsq)(CPUState *env, uint64_t a, uint64_t b)
{
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
......
target-arm/machine.c
浏览文件 @ a3ce3668
......@@ -44,6 +44,12 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c7_par);
qemu_put_be32(f, env->cp15.c9_insn);
qemu_put_be32(f, env->cp15.c9_data);
qemu_put_be32(f, env->cp15.c9_pmcr);
qemu_put_be32(f, env->cp15.c9_pmcnten);
qemu_put_be32(f, env->cp15.c9_pmovsr);
qemu_put_be32(f, env->cp15.c9_pmxevtyper);
qemu_put_be32(f, env->cp15.c9_pmuserenr);
qemu_put_be32(f, env->cp15.c9_pminten);
qemu_put_be32(f, env->cp15.c13_fcse);
qemu_put_be32(f, env->cp15.c13_context);
qemu_put_be32(f, env->cp15.c13_tls1);
......@@ -152,6 +158,12 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c7_par = qemu_get_be32(f);
env->cp15.c9_insn = qemu_get_be32(f);
env->cp15.c9_data = qemu_get_be32(f);
env->cp15.c9_pmcr = qemu_get_be32(f);
env->cp15.c9_pmcnten = qemu_get_be32(f);
env->cp15.c9_pmovsr = qemu_get_be32(f);
env->cp15.c9_pmxevtyper = qemu_get_be32(f);
env->cp15.c9_pmuserenr = qemu_get_be32(f);
env->cp15.c9_pminten = qemu_get_be32(f);
env->cp15.c13_fcse = qemu_get_be32(f);
env->cp15.c13_context = qemu_get_be32(f);
env->cp15.c13_tls1 = qemu_get_be32(f);
......
target-arm/neon_helper.c
浏览文件 @ a3ce3668
此差异已折叠。
target-arm/translate.c
浏览文件 @ a3ce3668
此差异已折叠。
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