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提交 a18ad893 编写于 作者: R Richard Henderson 提交者： Richard Henderson
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target-alpha: All ISA checks to use TB->FLAGS. 

We had two different methods in use, both of which referenced ENV,
and neither of which indicated to the generic code when different
compilation modes are not compatible.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
上级 21d2beaa
隐藏空白更改
内联 并排
Showing with 229 addition and 181 deletion
target-alpha/cpu.h
浏览文件 @ a18ad893
...@@ -418,12 +418,40 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env); ...@@ -418,12 +418,40 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env);
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
extern void swap_shadow_regs(CPUState *env); extern void swap_shadow_regs(CPUState *env);
/* Bits in TB->FLAGS that control how translation is processed. */
enum {
TB_FLAGS_PAL_MODE = 1,
TB_FLAGS_FEN = 2,
TB_FLAGS_USER_MODE = 8,
TB_FLAGS_AMASK_SHIFT = 4,
TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags) target_ulong *cs_base, int *pflags)
{ {
int flags = 0;
*pc = env->pc; *pc = env->pc;
*cs_base = 0; *cs_base = 0;
*flags = env->ps;
if (env->pal_mode) {
flags = TB_FLAGS_PAL_MODE;
} else {
flags = env->ps & PS_USER_MODE;
}
if (env->fen) {
flags |= TB_FLAGS_FEN;
}
flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
*pflags = flags;
} }
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
......
target-alpha/translate.c
浏览文件 @ a18ad893
...@@ -47,10 +47,6 @@ struct DisasContext { ...@@ -47,10 +47,6 @@ struct DisasContext {
CPUAlphaState *env; CPUAlphaState *env;
uint64_t pc; uint64_t pc;
int mem_idx; int mem_idx;
#if !defined (CONFIG_USER_ONLY)
int pal_mode;
#endif
uint32_t amask;
/* Current rounding mode for this TB. */ /* Current rounding mode for this TB. */
int tb_rm; int tb_rm;
...@@ -1654,20 +1650,22 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -1654,20 +1650,22 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x0A: case 0x0A:
/* LDBU */ /* LDBU */
if (!(ctx->amask & AMASK_BWX)) if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
goto invalid_opc; gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break;
break; }
goto invalid_opc;
case 0x0B: case 0x0B:
/* LDQ_U */ /* LDQ_U */
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
break; break;
case 0x0C: case 0x0C:
/* LDWU */ /* LDWU */
if (!(ctx->amask & AMASK_BWX)) if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
goto invalid_opc; gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); break;
break; }
goto invalid_opc;
case 0x0D: case 0x0D:
/* STW */ /* STW */
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
...@@ -2071,20 +2069,12 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2071,20 +2069,12 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x61: case 0x61:
/* AMASK */ /* AMASK */
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (islit) uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT;
tcg_gen_movi_i64(cpu_ir[rc], lit);
else if (islit) {
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); tcg_gen_movi_i64(cpu_ir[rc], lit & ~amask);
switch (ctx->env->implver) { } else {
case IMPLVER_2106x: tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rb], ~amask);
/* EV4, EV45, LCA, LCA45 & EV5 */
break;
case IMPLVER_21164:
case IMPLVER_21264:
case IMPLVER_21364:
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rc],
~(uint64_t)ctx->amask);
break;
} }
} }
break; break;
...@@ -2298,8 +2288,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2298,8 +2288,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch (fpfn) { /* fn11 & 0x3F */ switch (fpfn) { /* fn11 & 0x3F */
case 0x04: case 0x04:
/* ITOFS */ /* ITOFS */
if (!(ctx->amask & AMASK_FIX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (ra != 31) { if (ra != 31) {
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
...@@ -2312,20 +2303,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2312,20 +2303,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x0A: case 0x0A:
/* SQRTF */ /* SQRTF */
if (!(ctx->amask & AMASK_FIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
goto invalid_opc; gen_fsqrtf(rb, rc);
gen_fsqrtf(rb, rc); break;
break; }
goto invalid_opc;
case 0x0B: case 0x0B:
/* SQRTS */ /* SQRTS */
if (!(ctx->amask & AMASK_FIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
goto invalid_opc; gen_fsqrts(ctx, rb, rc, fn11);
gen_fsqrts(ctx, rb, rc, fn11); break;
break; }
goto invalid_opc;
case 0x14: case 0x14:
/* ITOFF */ /* ITOFF */
if (!(ctx->amask & AMASK_FIX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (ra != 31) { if (ra != 31) {
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
...@@ -2338,8 +2332,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2338,8 +2332,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x24: case 0x24:
/* ITOFT */ /* ITOFT */
if (!(ctx->amask & AMASK_FIX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (ra != 31) if (ra != 31)
tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
...@@ -2349,16 +2344,18 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2349,16 +2344,18 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x2A: case 0x2A:
/* SQRTG */ /* SQRTG */
if (!(ctx->amask & AMASK_FIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
goto invalid_opc; gen_fsqrtg(rb, rc);
gen_fsqrtg(rb, rc); break;
break; }
goto invalid_opc;
case 0x02B: case 0x02B:
/* SQRTT */ /* SQRTT */
if (!(ctx->amask & AMASK_FIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
goto invalid_opc; gen_fsqrtt(ctx, rb, rc, fn11);
gen_fsqrtt(ctx, rb, rc, fn11); break;
break; }
goto invalid_opc;
default: default:
goto invalid_opc; goto invalid_opc;
} }
...@@ -2660,7 +2657,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2660,7 +2657,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x19: case 0x19:
/* HW_MFPR (PALcode) */ /* HW_MFPR (PALcode) */
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (ctx->pal_mode) { if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
gen_mfpr(ra, insn & 0xffff); gen_mfpr(ra, insn & 0xffff);
break; break;
} }
...@@ -2681,13 +2678,15 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2681,13 +2678,15 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x1B: case 0x1B:
/* HW_LD (PALcode) */ /* HW_LD (PALcode) */
#if defined (CONFIG_USER_ONLY) #ifndef CONFIG_USER_ONLY
goto invalid_opc; if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
#else TCGv addr;
if (!ctx->pal_mode)
goto invalid_opc; if (ra == 31) {
if (ra != 31) { break;
TCGv addr = tcg_temp_new(); }
addr = tcg_temp_new();
if (rb != 31) if (rb != 31)
tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
else else
...@@ -2754,15 +2753,17 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2754,15 +2753,17 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
} }
tcg_temp_free(addr); tcg_temp_free(addr);
break;
} }
break;
#endif #endif
goto invalid_opc;
case 0x1C: case 0x1C:
switch (fn7) { switch (fn7) {
case 0x00: case 0x00:
/* SEXTB */ /* SEXTB */
if (!(ctx->amask & AMASK_BWX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_BWX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (islit) if (islit)
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
...@@ -2772,138 +2773,164 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2772,138 +2773,164 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x01: case 0x01:
/* SEXTW */ /* SEXTW */
if (!(ctx->amask & AMASK_BWX)) if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
goto invalid_opc; if (likely(rc != 31)) {
if (likely(rc != 31)) { if (islit) {
if (islit) tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); } else {
else tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); }
}
break;
} }
break; goto invalid_opc;
case 0x30: case 0x30:
/* CTPOP */ /* CTPOP */
if (!(ctx->amask & AMASK_CIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
goto invalid_opc; if (likely(rc != 31)) {
if (likely(rc != 31)) { if (islit) {
if (islit) tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); } else {
else gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); }
}
break;
} }
break; goto invalid_opc;
case 0x31: case 0x31:
/* PERR */ /* PERR */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_perr(ra, rb, rc, islit, lit);
gen_perr(ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x32: case 0x32:
/* CTLZ */ /* CTLZ */
if (!(ctx->amask & AMASK_CIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
goto invalid_opc; if (likely(rc != 31)) {
if (likely(rc != 31)) { if (islit) {
if (islit) tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); } else {
else gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); }
}
break;
} }
break; goto invalid_opc;
case 0x33: case 0x33:
/* CTTZ */ /* CTTZ */
if (!(ctx->amask & AMASK_CIX)) if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
goto invalid_opc; if (likely(rc != 31)) {
if (likely(rc != 31)) { if (islit) {
if (islit) tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); } else {
else gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); }
}
break;
} }
break; goto invalid_opc;
case 0x34: case 0x34:
/* UNPKBW */ /* UNPKBW */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; if (real_islit || ra != 31) {
if (real_islit || ra != 31) goto invalid_opc;
goto invalid_opc; }
gen_unpkbw (rb, rc); gen_unpkbw(rb, rc);
break; break;
}
goto invalid_opc;
case 0x35: case 0x35:
/* UNPKBL */ /* UNPKBL */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; if (real_islit || ra != 31) {
if (real_islit || ra != 31) goto invalid_opc;
goto invalid_opc; }
gen_unpkbl (rb, rc); gen_unpkbl(rb, rc);
break; break;
}
goto invalid_opc;
case 0x36: case 0x36:
/* PKWB */ /* PKWB */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; if (real_islit || ra != 31) {
if (real_islit || ra != 31) goto invalid_opc;
goto invalid_opc; }
gen_pkwb (rb, rc); gen_pkwb(rb, rc);
break; break;
}
goto invalid_opc;
case 0x37: case 0x37:
/* PKLB */ /* PKLB */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; if (real_islit || ra != 31) {
if (real_islit || ra != 31) goto invalid_opc;
goto invalid_opc; }
gen_pklb (rb, rc); gen_pklb(rb, rc);
break; break;
}
goto invalid_opc;
case 0x38: case 0x38:
/* MINSB8 */ /* MINSB8 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_minsb8(ra, rb, rc, islit, lit);
gen_minsb8 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x39: case 0x39:
/* MINSW4 */ /* MINSW4 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_minsw4(ra, rb, rc, islit, lit);
gen_minsw4 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3A: case 0x3A:
/* MINUB8 */ /* MINUB8 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_minub8(ra, rb, rc, islit, lit);
gen_minub8 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3B: case 0x3B:
/* MINUW4 */ /* MINUW4 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_minuw4(ra, rb, rc, islit, lit);
gen_minuw4 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3C: case 0x3C:
/* MAXUB8 */ /* MAXUB8 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_maxub8(ra, rb, rc, islit, lit);
gen_maxub8 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3D: case 0x3D:
/* MAXUW4 */ /* MAXUW4 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_maxuw4(ra, rb, rc, islit, lit);
gen_maxuw4 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3E: case 0x3E:
/* MAXSB8 */ /* MAXSB8 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_maxsb8(ra, rb, rc, islit, lit);
gen_maxsb8 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x3F: case 0x3F:
/* MAXSW4 */ /* MAXSW4 */
if (!(ctx->amask & AMASK_MVI)) if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
goto invalid_opc; gen_maxsw4(ra, rb, rc, islit, lit);
gen_maxsw4 (ra, rb, rc, islit, lit); break;
break; }
goto invalid_opc;
case 0x70: case 0x70:
/* FTOIT */ /* FTOIT */
if (!(ctx->amask & AMASK_FIX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (likely(rc != 31)) { if (likely(rc != 31)) {
if (ra != 31) if (ra != 31)
tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
...@@ -2913,8 +2940,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2913,8 +2940,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x78: case 0x78:
/* FTOIS */ /* FTOIS */
if (!(ctx->amask & AMASK_FIX)) if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) {
goto invalid_opc; goto invalid_opc;
}
if (rc != 31) { if (rc != 31) {
TCGv_i32 tmp1 = tcg_temp_new_i32(); TCGv_i32 tmp1 = tcg_temp_new_i32();
if (ra != 31) if (ra != 31)
...@@ -2935,41 +2963,36 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -2935,41 +2963,36 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x1D: case 0x1D:
/* HW_MTPR (PALcode) */ /* HW_MTPR (PALcode) */
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (ctx->pal_mode) { if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
gen_mtpr(ra, insn & 0xffff); gen_mtpr(rb, insn & 0xffff);
break; break;
} }
#endif #endif
goto invalid_opc; goto invalid_opc;
case 0x1E: case 0x1E:
/* HW_RET (PALcode) */ /* HW_RET (PALcode) */
#if defined (CONFIG_USER_ONLY) #ifndef CONFIG_USER_ONLY
goto invalid_opc; if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
#else if (rb == 31) {
if (!ctx->pal_mode) /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
goto invalid_opc; address from EXC_ADDR. This turns out to be useful for our
if (rb == 31) { emulation PALcode, so continue to accept it. */
/* Pre-EV6 CPUs interpreted this as HW_REI, loading the return TCGv tmp = tcg_temp_new();
address from EXC_ADDR. This turns out to be useful for our tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr));
emulation PALcode, so continue to accept it. */ gen_helper_hw_ret(tmp);
TCGv tmp = tcg_temp_new(); tcg_temp_free(tmp);
/* FIXME: Get exc_addr. */ } else {
gen_helper_hw_ret(tmp); gen_helper_hw_ret(cpu_ir[rb]);
tcg_temp_free(tmp); }
} else { ret = EXIT_PC_UPDATED;
gen_helper_hw_ret(cpu_ir[rb]); break;
} }
ret = EXIT_PC_UPDATED;
break;
#endif #endif
goto invalid_opc;
case 0x1F: case 0x1F:
/* HW_ST (PALcode) */ /* HW_ST (PALcode) */
#if defined (CONFIG_USER_ONLY) #ifndef CONFIG_USER_ONLY
goto invalid_opc; if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
#else
if (!ctx->pal_mode)
goto invalid_opc;
else {
TCGv addr, val; TCGv addr, val;
addr = tcg_temp_new(); addr = tcg_temp_new();
if (rb != 31) if (rb != 31)
...@@ -3039,9 +3062,10 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) ...@@ -3039,9 +3062,10 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
if (ra == 31) if (ra == 31)
tcg_temp_free(val); tcg_temp_free(val);
tcg_temp_free(addr); tcg_temp_free(addr);
break;
} }
break;
#endif #endif
goto invalid_opc;
case 0x20: case 0x20:
/* LDF */ /* LDF */
gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
...@@ -3192,11 +3216,7 @@ static inline void gen_intermediate_code_internal(CPUState *env, ...@@ -3192,11 +3216,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
ctx.tb = tb; ctx.tb = tb;
ctx.env = env; ctx.env = env;
ctx.pc = pc_start; ctx.pc = pc_start;
ctx.amask = env->amask;
ctx.mem_idx = cpu_mmu_index(env); ctx.mem_idx = cpu_mmu_index(env);
#if !defined (CONFIG_USER_ONLY)
ctx.pal_mode = env->pal_mode;
#endif
/* ??? Every TB begins with unset rounding mode, to be initialized on /* ??? Every TB begins with unset rounding mode, to be initialized on
the first fp insn of the TB. Alternately we could define a proper the first fp insn of the TB. Alternately we could define a proper
......
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