Implementing dmfc/dmtc.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/cpu.h

@@ -44,7 +44,7 @@ union fpr_t {
 typedef struct tlb_t tlb_t;
 struct tlb_t {
     target_ulong VPN;
-    uint_fast32_t PageMask;
+    uint32_t PageMask;
     uint_fast8_t ASID;
     uint_fast16_t G:1;
     uint_fast16_t C0:3;
@@ -110,20 +110,20 @@ struct CPUMIPSState {
     tlb_t tlb[MIPS_TLB_MAX];
     uint32_t tlb_in_use;
 #endif
-    uint32_t CP0_index;
-    uint32_t CP0_random;
-    uint64_t CP0_EntryLo0;
-    uint64_t CP0_EntryLo1;
-    uint64_t CP0_Context;
-    uint32_t CP0_PageMask;
-    uint32_t CP0_PageGrain;
-    uint32_t CP0_Wired;
-    uint32_t CP0_HWREna;
+    int32_t CP0_Index;
+    int32_t CP0_Random;
+    target_ulong CP0_EntryLo0;
+    target_ulong CP0_EntryLo1;
+    target_ulong CP0_Context;
+    int32_t CP0_PageMask;
+    int32_t CP0_PageGrain;
+    int32_t CP0_Wired;
+    int32_t CP0_HWREna;
     target_ulong CP0_BadVAddr;
-    uint32_t CP0_Count;
-    uint64_t CP0_EntryHi;
-    uint32_t CP0_Compare;
-    uint32_t CP0_Status;
+    int32_t CP0_Count;
+    target_ulong CP0_EntryHi;
+    int32_t CP0_Compare;
+    int32_t CP0_Status;
 #define CP0St_CU3   31
 #define CP0St_CU2   30
 #define CP0St_CU1   29
@@ -146,9 +146,10 @@ struct CPUMIPSState {
 #define CP0St_ERL   2
 #define CP0St_EXL   1
 #define CP0St_IE    0
-    uint32_t CP0_IntCtl;
-    uint32_t CP0_SRSCtl;
-    uint32_t CP0_Cause;
+    int32_t CP0_IntCtl;
+    int32_t CP0_SRSCtl;
+    int32_t CP0_SRSMap;
+    int32_t CP0_Cause;
 #define CP0Ca_BD   31
 #define CP0Ca_TI   30
 #define CP0Ca_CE   28
@@ -159,9 +160,9 @@ struct CPUMIPSState {
 #define CP0Ca_IP    8
 #define CP0Ca_EC    2
     target_ulong CP0_EPC;
-    uint32_t CP0_PRid;
+    int32_t CP0_PRid;
     target_ulong CP0_EBase;
-    uint32_t CP0_Config0;
+    int32_t CP0_Config0;
 #define CP0C0_M    31
 #define CP0C0_K23  28
 #define CP0C0_KU   25
@@ -174,7 +175,7 @@ struct CPUMIPSState {
 #define CP0C0_MT   7
 #define CP0C0_VI   3
 #define CP0C0_K0   0
-    uint32_t CP0_Config1;
+    int32_t CP0_Config1;
 #define CP0C1_M    31
 #define CP0C1_MMU  25
 #define CP0C1_IS   22
@@ -190,7 +191,7 @@ struct CPUMIPSState {
 #define CP0C1_CA   2
 #define CP0C1_EP   1
 #define CP0C1_FP   0
-    uint32_t CP0_Config2;
+    int32_t CP0_Config2;
 #define CP0C2_M    31
 #define CP0C2_TU   28
 #define CP0C2_TS   24
@@ -200,7 +201,7 @@ struct CPUMIPSState {
 #define CP0C2_SS   8
 #define CP0C2_SL   4
 #define CP0C2_SA   0
-    uint32_t CP0_Config3;
+    int32_t CP0_Config3;
 #define CP0C3_M    31
 #define CP0C3_DSPP 10
 #define CP0C3_LPA  7
@@ -211,11 +212,11 @@ struct CPUMIPSState {
 #define CP0C3_SM   1
 #define CP0C3_TL   0
     target_ulong CP0_LLAddr;
-    uint32_t CP0_WatchLo;
-    uint32_t CP0_WatchHi;
-    uint32_t CP0_XContext;
-    uint32_t CP0_Framemask;
-    uint32_t CP0_Debug;
+    target_ulong CP0_WatchLo;
+    int32_t CP0_WatchHi;
+    target_ulong CP0_XContext;
+    int32_t CP0_Framemask;
+    int32_t CP0_Debug;
 #define CPDB_DBD   31
 #define CP0DB_DM   30
 #define CP0DB_LSNM 28
@@ -235,13 +236,13 @@ struct CPUMIPSState {
 #define CP0DB_DBp  1
 #define CP0DB_DSS  0
     target_ulong CP0_DEPC;
-    uint32_t CP0_Performance0;
-    uint32_t CP0_TagLo;
-    uint32_t CP0_DataLo;
-    uint32_t CP0_TagHi;
-    uint32_t CP0_DataHi;
+    int32_t CP0_Performance0;
+    int32_t CP0_TagLo;
+    int32_t CP0_DataLo;
+    int32_t CP0_TagHi;
+    int32_t CP0_DataHi;
     target_ulong CP0_ErrorEPC;
-    uint32_t CP0_DESAVE;
+    int32_t CP0_DESAVE;
     /* Qemu */
     int interrupt_request;
     jmp_buf jmp_env;

target-mips/op.c

@@ -1032,7 +1032,7 @@ void op_jnz_T2 (void)
 /* CP0 functions */
 void op_mfc0_index (void)
 {
-    T0 = (int32_t)(env->CP0_index);
+    T0 = env->CP0_Index;
     RETURN();
 }
 
@@ -1044,49 +1044,49 @@ void op_mfc0_random (void)
 
 void op_mfc0_entrylo0 (void)
 {
-    T0 = env->CP0_EntryLo0;
+    T0 = (int32_t)env->CP0_EntryLo0;
     RETURN();
 }
 
 void op_mfc0_entrylo1 (void)
 {
-    T0 = env->CP0_EntryLo1;
+    T0 = (int32_t)env->CP0_EntryLo1;
     RETURN();
 }
 
 void op_mfc0_context (void)
 {
-    T0 = env->CP0_Context;
+    T0 = (int32_t)env->CP0_Context;
     RETURN();
 }
 
 void op_mfc0_pagemask (void)
 {
-    T0 = (int32_t)env->CP0_PageMask;
+    T0 = env->CP0_PageMask;
     RETURN();
 }
 
 void op_mfc0_pagegrain (void)
 {
-    T0 = (int32_t)env->CP0_PageGrain;
+    T0 = env->CP0_PageGrain;
     RETURN();
 }
 
 void op_mfc0_wired (void)
 {
-    T0 = (int32_t)env->CP0_Wired;
+    T0 = env->CP0_Wired;
     RETURN();
 }
 
 void op_mfc0_hwrena (void)
 {
-    T0 = (int32_t)env->CP0_HWREna;
+    T0 = env->CP0_HWREna;
     RETURN();
 }
 
 void op_mfc0_badvaddr (void)
 {
-    T0 = env->CP0_BadVAddr;
+    T0 = (int32_t)env->CP0_BadVAddr;
     RETURN();
 }
 
@@ -1098,19 +1098,19 @@ void op_mfc0_count (void)
 
 void op_mfc0_entryhi (void)
 {
-    T0 = env->CP0_EntryHi;
+    T0 = (int32_t)env->CP0_EntryHi;
     RETURN();
 }
 
 void op_mfc0_compare (void)
 {
-    T0 = (int32_t)env->CP0_Compare;
+    T0 = env->CP0_Compare;
     RETURN();
 }
 
 void op_mfc0_status (void)
 {
-    T0 = (int32_t)env->CP0_Status;
+    T0 = env->CP0_Status;
     if (env->hflags & MIPS_HFLAG_UM)
         T0 |= (1 << CP0St_UM);
     if (env->hflags & MIPS_HFLAG_ERL)
@@ -1122,67 +1122,73 @@ void op_mfc0_status (void)
 
 void op_mfc0_intctl (void)
 {
-    T0 = (int32_t)env->CP0_IntCtl;
+    T0 = env->CP0_IntCtl;
     RETURN();
 }
 
 void op_mfc0_srsctl (void)
 {
-    T0 = (int32_t)env->CP0_SRSCtl;
+    T0 = env->CP0_SRSCtl;
+    RETURN();
+}
+
+void op_mfc0_srsmap (void)
+{
+    T0 = env->CP0_SRSMap;
     RETURN();
 }
 
 void op_mfc0_cause (void)
 {
-    T0 = (int32_t)env->CP0_Cause;
+    T0 = env->CP0_Cause;
     RETURN();
 }
 
 void op_mfc0_epc (void)
 {
-    T0 = env->CP0_EPC;
+    T0 = (int32_t)env->CP0_EPC;
     RETURN();
 }
 
 void op_mfc0_prid (void)
 {
-    T0 = (int32_t)env->CP0_PRid;
+    T0 = env->CP0_PRid;
     RETURN();
 }
 
 void op_mfc0_ebase (void)
 {
-    T0 = env->CP0_EBase;
+    T0 = (int32_t)env->CP0_EBase;
     RETURN();
 }
 
 void op_mfc0_config0 (void)
 {
-    T0 = (int32_t)env->CP0_Config0;
+    T0 = env->CP0_Config0;
     RETURN();
 }
 
 void op_mfc0_config1 (void)
 {
-    T0 = (int32_t)env->CP0_Config1;
+    T0 = env->CP0_Config1;
     RETURN();
 }
 
 void op_mfc0_config2 (void)
 {
-    T0 = (int32_t)env->CP0_Config2;
+    T0 = env->CP0_Config2;
     RETURN();
 }
 
 void op_mfc0_config3 (void)
 {
-    T0 = (int32_t)env->CP0_Config3;
+    T0 = env->CP0_Config3;
     RETURN();
 }
 
 void op_mfc0_lladdr (void)
 {
-    T0 = env->CP0_LLAddr >> 4;
+    T0 = (int32_t)env->CP0_LLAddr >> 4;
     RETURN();
 }
 
@@ -1194,13 +1200,13 @@ void op_mfc0_watchlo0 (void)
 
 void op_mfc0_watchhi0 (void)
 {
-    T0 = (int32_t)env->CP0_WatchHi;
+    T0 = env->CP0_WatchHi;
     RETURN();
 }
 
 void op_mfc0_xcontext (void)
 {
-    T0 = env->CP0_XContext;
+    T0 = (int32_t)env->CP0_XContext;
     RETURN();
 }
 
@@ -1212,7 +1218,7 @@ void op_mfc0_framemask (void)
 
 void op_mfc0_debug (void)
 {
-    T0 = (int32_t)env->CP0_Debug;
+    T0 = env->CP0_Debug;
     if (env->hflags & MIPS_HFLAG_DM)
         T0 |= 1 << CP0DB_DM;
     RETURN();
@@ -1220,55 +1226,55 @@ void op_mfc0_debug (void)
 
 void op_mfc0_depc (void)
 {
-    T0 = env->CP0_DEPC;
+    T0 = (int32_t)env->CP0_DEPC;
     RETURN();
 }
 
 void op_mfc0_performance0 (void)
 {
-    T0 = (int32_t)env->CP0_Performance0;
+    T0 = env->CP0_Performance0;
     RETURN();
 }
 
 void op_mfc0_taglo (void)
 {
-    T0 = (int32_t)env->CP0_TagLo;
+    T0 = env->CP0_TagLo;
     RETURN();
 }
 
 void op_mfc0_datalo (void)
 {
-    T0 = (int32_t)env->CP0_DataLo;
+    T0 = env->CP0_DataLo;
     RETURN();
 }
 
 void op_mfc0_taghi (void)
 {
-    T0 = (int32_t)env->CP0_TagHi;
+    T0 = env->CP0_TagHi;
     RETURN();
 }
 
 void op_mfc0_datahi (void)
 {
-    T0 = (int32_t)env->CP0_DataHi;
+    T0 = env->CP0_DataHi;
     RETURN();
 }
 
 void op_mfc0_errorepc (void)
 {
-    T0 = env->CP0_ErrorEPC;
+    T0 = (int32_t)env->CP0_ErrorEPC;
     RETURN();
 }
 
 void op_mfc0_desave (void)
 {
-    T0 = (int32_t)env->CP0_DESAVE;
+    T0 = env->CP0_DESAVE;
     RETURN();
 }
 
 void op_mtc0_index (void)
 {
-    env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
+    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
     RETURN();
 }
 
@@ -1276,7 +1282,7 @@ void op_mtc0_entrylo0 (void)
 {
     /* Large physaddr not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo0 = T0 & (int32_t)0x3FFFFFFF;
+    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
     RETURN();
 }
 
@@ -1284,7 +1290,7 @@ void op_mtc0_entrylo1 (void)
 {
     /* Large physaddr not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo1 = T0 & (int32_t)0x3FFFFFFF;
+    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
     RETURN();
 }
 
@@ -1334,7 +1340,7 @@ void op_mtc0_entryhi (void)
 
     /* 1k pages not implemented */
     /* Ignore MIPS64 TLB for now */
-    val = T0 & (int32_t)0xFFFFE0FF;
+    val = (int32_t)T0 & 0xFFFFE0FF;
     old = env->CP0_EntryHi;
     env->CP0_EntryHi = val;
     /* If the ASID changes, flush qemu's TLB.  */
@@ -1353,7 +1359,7 @@ void op_mtc0_status (void)
 {
     uint32_t val, old, mask;
 
-    val = T0 & (int32_t)0xFA78FF01;
+    val = (int32_t)T0 & 0xFA78FF01;
     old = env->CP0_Status;
     if (T0 & (1 << CP0St_UM))
         env->hflags |= MIPS_HFLAG_UM;
@@ -1400,6 +1406,13 @@ void op_mtc0_srsctl (void)
     RETURN();
 }
 
+void op_mtc0_srsmap (void)
+{
+    /* shadow registers not implemented */
+    env->CP0_SRSMap = 0;
+    RETURN();
+}
+
 void op_mtc0_cause (void)
 {
     uint32_t val, old;
@@ -1423,7 +1436,7 @@ void op_mtc0_cause (void)
 
 void op_mtc0_epc (void)
 {
-    env->CP0_EPC = T0;
+    env->CP0_EPC = (int32_t)T0;
     RETURN();
 }
 
@@ -1455,7 +1468,7 @@ void op_mtc0_config2 (void)
 
 void op_mtc0_watchlo0 (void)
 {
-    env->CP0_WatchLo = T0;
+    env->CP0_WatchLo = (int32_t)T0;
     RETURN();
 }
 
@@ -1467,7 +1480,7 @@ void op_mtc0_watchhi0 (void)
 
 void op_mtc0_xcontext (void)
 {
-    env->CP0_XContext = T0; /* XXX */
+    env->CP0_XContext = (int32_t)T0; /* XXX */
     RETURN();
 }
 
@@ -1489,7 +1502,7 @@ void op_mtc0_debug (void)
 
 void op_mtc0_depc (void)
 {
-    env->CP0_DEPC = T0;
+    env->CP0_DEPC = (int32_t)T0;
     RETURN();
 }
 
@@ -1501,7 +1514,7 @@ void op_mtc0_performance0 (void)
 
 void op_mtc0_taglo (void)
 {
-    env->CP0_TagLo = T0 & (int32_t)0xFFFFFCF6;
+    env->CP0_TagLo = T0 & 0xFFFFFCF6;
     RETURN();
 }
 
@@ -1525,7 +1538,7 @@ void op_mtc0_datahi (void)
 
 void op_mtc0_errorepc (void)
 {
-    env->CP0_ErrorEPC = T0;
+    env->CP0_ErrorEPC = (int32_t)T0;
     RETURN();
 }
 
@@ -1535,6 +1548,139 @@ void op_mtc0_desave (void)
     RETURN();
 }
 
+void op_dmfc0_entrylo0 (void)
+{
+    T0 = env->CP0_EntryLo0;
+    RETURN();
+}
+
+void op_dmfc0_entrylo1 (void)
+{
+    T0 = env->CP0_EntryLo1;
+    RETURN();
+}
+
+void op_dmfc0_context (void)
+{
+    T0 = env->CP0_Context;
+    RETURN();
+}
+
+void op_dmfc0_badvaddr (void)
+{
+    T0 = env->CP0_BadVAddr;
+    RETURN();
+}
+
+void op_dmfc0_entryhi (void)
+{
+    T0 = env->CP0_EntryHi;
+    RETURN();
+}
+
+void op_dmfc0_epc (void)
+{
+    T0 = env->CP0_EPC;
+    RETURN();
+}
+
+void op_dmfc0_ebase (void)
+{
+    T0 = env->CP0_EBase;
+    RETURN();
+}
+
+void op_dmfc0_lladdr (void)
+{
+    T0 = env->CP0_LLAddr >> 4;
+    RETURN();
+}
+
+void op_dmfc0_watchlo0 (void)
+{
+    T0 = env->CP0_WatchLo;
+    RETURN();
+}
+
+void op_dmfc0_xcontext (void)
+{
+    T0 = env->CP0_XContext;
+    RETURN();
+}
+
+void op_dmfc0_depc (void)
+{
+    T0 = env->CP0_DEPC;
+    RETURN();
+}
+
+void op_dmfc0_errorepc (void)
+{
+    T0 = env->CP0_ErrorEPC;
+    RETURN();
+}
+
+void op_dmtc0_entrylo0 (void)
+{
+    /* Large physaddr not implemented */
+    /* 1k pages not implemented */
+    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
+    RETURN();
+}
+
+void op_dmtc0_entrylo1 (void)
+{
+    /* Large physaddr not implemented */
+    /* 1k pages not implemented */
+    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
+    RETURN();
+}
+
+void op_dmtc0_context (void)
+{
+    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
+    RETURN();
+}
+
+void op_dmtc0_epc (void)
+{
+    env->CP0_EPC = T0;
+    RETURN();
+}
+
+void op_dmtc0_ebase (void)
+{
+    /* vectored interrupts not implemented */
+    /* Multi-CPU not implemented */
+    /* XXX: 64bit addressing broken */
+    env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
+    RETURN();
+}
+
+void op_dmtc0_watchlo0 (void)
+{
+    env->CP0_WatchLo = T0;
+    RETURN();
+}
+
+void op_dmtc0_xcontext (void)
+{
+    env->CP0_XContext = T0; /* XXX */
+    RETURN();
+}
+
+void op_dmtc0_depc (void)
+{
+    env->CP0_DEPC = T0;
+    RETURN();
+}
+
+void op_dmtc0_errorepc (void)
+{
+    env->CP0_ErrorEPC = T0;
+    RETURN();
+}
+
 #ifdef MIPS_USES_FPU
 
 #if 0

target-mips/op_helper.c

@@ -411,10 +411,10 @@ void do_tlbwi (void)
        that might be a further win.  */
     mips_tlb_flush_extra (env, MIPS_TLB_NB);
 
-    /* Wildly undefined effects for CP0_index containing a too high value and
+    /* Wildly undefined effects for CP0_Index containing a too high value and
        MIPS_TLB_NB not being a power of two.  But so does real silicon.  */
-    invalidate_tlb(env, env->CP0_index & (MIPS_TLB_NB - 1), 0);
-    fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
+    invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
+    fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
 }
 
 void do_tlbwr (void)
@@ -439,7 +439,7 @@ void do_tlbp (void)
         /* Check ASID, virtual page number & size */
         if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
             /* TLB match */
-            env->CP0_index = i;
+            env->CP0_Index = i;
             break;
         }
     }
@@ -455,7 +455,7 @@ void do_tlbp (void)
 	    }
 	}
 
-        env->CP0_index |= 0x80000000;
+        env->CP0_Index |= 0x80000000;
     }
 }
 
@@ -465,7 +465,7 @@ void do_tlbr (void)
     uint8_t ASID;
 
     ASID = env->CP0_EntryHi & 0xFF;
-    tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
+    tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
 
     /* If this will change the current ASID, flush qemu's TLB.  */
     if (ASID != tlb->ASID)