Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
qemu
提交
97aff481
Q
qemu
项目概览
openeuler
/
qemu
通知
10
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
Q
qemu
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
97aff481
编写于
5月 14, 2009
作者:
P
Paul Brook
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
PL190 qdev conversion
Signed-off-by:
N
Paul Brook
<
paul@codesourcery.com
>
上级
cfb9de9c
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
41 addition
and
28 deletion
+41
-28
hw/pl190.c
hw/pl190.c
+15
-11
hw/primecell.h
hw/primecell.h
+1
-4
hw/realview.c
hw/realview.c
+1
-1
hw/versatile_pci.c
hw/versatile_pci.c
+9
-6
hw/versatilepb.c
hw/versatilepb.c
+15
-6
未找到文件。
hw/pl190.c
浏览文件 @
97aff481
...
@@ -7,8 +7,7 @@
...
@@ -7,8 +7,7 @@
* This code is licenced under the GPL.
* This code is licenced under the GPL.
*/
*/
#include "hw.h"
#include "sysbus.h"
#include "primecell.h"
/* The number of virtual priority levels. 16 user vectors plus the
/* The number of virtual priority levels. 16 user vectors plus the
unvectored IRQ. Chained interrupts would require an additional level
unvectored IRQ. Chained interrupts would require an additional level
...
@@ -17,6 +16,7 @@
...
@@ -17,6 +16,7 @@
#define PL190_NUM_PRIO 17
#define PL190_NUM_PRIO 17
typedef
struct
{
typedef
struct
{
SysBusDevice
busdev
;
uint32_t
level
;
uint32_t
level
;
uint32_t
soft_level
;
uint32_t
soft_level
;
uint32_t
irq_enable
;
uint32_t
irq_enable
;
...
@@ -227,20 +227,24 @@ static void pl190_reset(pl190_state *s)
...
@@ -227,20 +227,24 @@ static void pl190_reset(pl190_state *s)
pl190_update_vectors
(
s
);
pl190_update_vectors
(
s
);
}
}
qemu_irq
*
pl190_init
(
uint32_t
base
,
qemu_irq
irq
,
qemu_irq
fiq
)
static
void
pl190_init
(
SysBusDevice
*
dev
)
{
{
pl190_state
*
s
;
pl190_state
*
s
=
FROM_SYSBUS
(
pl190_state
,
dev
);
qemu_irq
*
qi
;
int
iomemtype
;
int
iomemtype
;
s
=
(
pl190_state
*
)
qemu_mallocz
(
sizeof
(
pl190_state
));
iomemtype
=
cpu_register_io_memory
(
0
,
pl190_readfn
,
iomemtype
=
cpu_register_io_memory
(
0
,
pl190_readfn
,
pl190_writefn
,
s
);
pl190_writefn
,
s
);
cpu_register_physical_memory
(
base
,
0x0000
1000
,
iomemtype
);
sysbus_init_mmio
(
dev
,
0x
1000
,
iomemtype
);
q
i
=
qemu_allocate_irqs
(
pl190_set_irq
,
s
,
32
);
q
dev_init_irq_sink
(
&
dev
->
qdev
,
pl190_set_irq
,
32
);
s
->
irq
=
irq
;
s
ysbus_init_irq
(
dev
,
&
s
->
irq
)
;
s
->
fiq
=
fiq
;
s
ysbus_init_irq
(
dev
,
&
s
->
fiq
)
;
pl190_reset
(
s
);
pl190_reset
(
s
);
/* ??? Save/restore. */
/* ??? Save/restore. */
return
qi
;
}
}
static
void
pl190_register_devices
(
void
)
{
sysbus_register_dev
(
"pl190"
,
sizeof
(
pl190_state
),
pl190_init
);
}
device_init
(
pl190_register_devices
)
hw/primecell.h
浏览文件 @
97aff481
...
@@ -17,9 +17,6 @@ qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
...
@@ -17,9 +17,6 @@ qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
/* pl080.c */
/* pl080.c */
void
*
pl080_init
(
uint32_t
base
,
qemu_irq
irq
,
int
nchannels
);
void
*
pl080_init
(
uint32_t
base
,
qemu_irq
irq
,
int
nchannels
);
/* pl190.c */
qemu_irq
*
pl190_init
(
uint32_t
base
,
qemu_irq
irq
,
qemu_irq
fiq
);
/* realview_gic.c */
/* realview_gic.c */
qemu_irq
*
realview_gic_init
(
uint32_t
base
,
qemu_irq
parent_irq
);
qemu_irq
*
realview_gic_init
(
uint32_t
base
,
qemu_irq
parent_irq
);
...
@@ -30,6 +27,6 @@ extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
...
@@ -30,6 +27,6 @@ extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
void
arm_sysctl_init
(
uint32_t
base
,
uint32_t
sys_id
);
void
arm_sysctl_init
(
uint32_t
base
,
uint32_t
sys_id
);
/* versatile_pci.c */
/* versatile_pci.c */
PCIBus
*
pci_vpb_init
(
qemu_irq
*
pic
,
int
irq
,
int
realview
);
PCIBus
*
pci_vpb_init
(
qemu_irq
*
pic
,
int
realview
);
#endif
#endif
hw/realview.c
浏览文件 @
97aff481
...
@@ -100,7 +100,7 @@ static void realview_init(ram_addr_t ram_size,
...
@@ -100,7 +100,7 @@ static void realview_init(ram_addr_t ram_size,
sysbus_create_simple
(
"pl031"
,
0x10017000
,
pic
[
10
]);
sysbus_create_simple
(
"pl031"
,
0x10017000
,
pic
[
10
]);
pci_bus
=
pci_vpb_init
(
pic
,
48
,
1
);
pci_bus
=
pci_vpb_init
(
pic
+
48
,
1
);
if
(
usb_enabled
)
{
if
(
usb_enabled
)
{
usb_ohci_init_pci
(
pci_bus
,
3
,
-
1
);
usb_ohci_init_pci
(
pci_bus
,
3
,
-
1
);
}
}
...
...
hw/versatile_pci.c
浏览文件 @
97aff481
...
@@ -79,8 +79,6 @@ static CPUReadMemoryFunc *pci_vpb_config_read[] = {
...
@@ -79,8 +79,6 @@ static CPUReadMemoryFunc *pci_vpb_config_read[] = {
&
pci_vpb_config_readl
,
&
pci_vpb_config_readl
,
};
};
static
int
pci_vpb_irq
;
static
int
pci_vpb_map_irq
(
PCIDevice
*
d
,
int
irq_num
)
static
int
pci_vpb_map_irq
(
PCIDevice
*
d
,
int
irq_num
)
{
{
return
irq_num
;
return
irq_num
;
...
@@ -88,18 +86,23 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
...
@@ -88,18 +86,23 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
static
void
pci_vpb_set_irq
(
qemu_irq
*
pic
,
int
irq_num
,
int
level
)
static
void
pci_vpb_set_irq
(
qemu_irq
*
pic
,
int
irq_num
,
int
level
)
{
{
qemu_set_irq
(
pic
[
pci_vpb_irq
+
irq_num
],
level
);
qemu_set_irq
(
pic
[
irq_num
],
level
);
}
}
PCIBus
*
pci_vpb_init
(
qemu_irq
*
pic
,
int
irq
,
int
realview
)
PCIBus
*
pci_vpb_init
(
qemu_irq
*
pic
,
int
realview
)
{
{
PCIBus
*
s
;
PCIBus
*
s
;
PCIDevice
*
d
;
PCIDevice
*
d
;
int
mem_config
;
int
mem_config
;
uint32_t
base
;
uint32_t
base
;
const
char
*
name
;
const
char
*
name
;
qemu_irq
*
irqs
;
int
i
;
pci_vpb_irq
=
irq
;
irqs
=
qemu_mallocz
(
sizeof
(
qemu_irq
)
*
4
);
for
(
i
=
0
;
i
<
4
;
i
++
)
{
irqs
[
i
]
=
pic
[
i
];
}
if
(
realview
)
{
if
(
realview
)
{
base
=
0x60000000
;
base
=
0x60000000
;
name
=
"RealView EB PCI Controller"
;
name
=
"RealView EB PCI Controller"
;
...
@@ -107,7 +110,7 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
...
@@ -107,7 +110,7 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
base
=
0x40000000
;
base
=
0x40000000
;
name
=
"Versatile/PB PCI Controller"
;
name
=
"Versatile/PB PCI Controller"
;
}
}
s
=
pci_register_bus
(
pci_vpb_set_irq
,
pci_vpb_map_irq
,
pic
,
11
<<
3
,
4
);
s
=
pci_register_bus
(
pci_vpb_set_irq
,
pci_vpb_map_irq
,
irqs
,
11
<<
3
,
4
);
/* ??? Register memory space. */
/* ??? Register memory space. */
mem_config
=
cpu_register_io_memory
(
0
,
pci_vpb_config_read
,
mem_config
=
cpu_register_io_memory
(
0
,
pci_vpb_config_read
,
...
...
hw/versatilepb.c
浏览文件 @
97aff481
...
@@ -23,7 +23,7 @@ typedef struct vpb_sic_state
...
@@ -23,7 +23,7 @@ typedef struct vpb_sic_state
uint32_t
level
;
uint32_t
level
;
uint32_t
mask
;
uint32_t
mask
;
uint32_t
pic_enable
;
uint32_t
pic_enable
;
qemu_irq
*
parent
;
qemu_irq
parent
[
32
]
;
int
irq
;
int
irq
;
}
vpb_sic_state
;
}
vpb_sic_state
;
...
@@ -133,10 +133,13 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
...
@@ -133,10 +133,13 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
vpb_sic_state
*
s
;
vpb_sic_state
*
s
;
qemu_irq
*
qi
;
qemu_irq
*
qi
;
int
iomemtype
;
int
iomemtype
;
int
i
;
s
=
(
vpb_sic_state
*
)
qemu_mallocz
(
sizeof
(
vpb_sic_state
));
s
=
(
vpb_sic_state
*
)
qemu_mallocz
(
sizeof
(
vpb_sic_state
));
qi
=
qemu_allocate_irqs
(
vpb_sic_set_irq
,
s
,
32
);
qi
=
qemu_allocate_irqs
(
vpb_sic_set_irq
,
s
,
32
);
s
->
parent
=
parent
;
for
(
i
=
0
;
i
<
32
;
i
++
)
{
s
->
parent
[
i
]
=
parent
[
i
];
}
s
->
irq
=
irq
;
s
->
irq
=
irq
;
iomemtype
=
cpu_register_io_memory
(
0
,
vpb_sic_readfn
,
iomemtype
=
cpu_register_io_memory
(
0
,
vpb_sic_readfn
,
vpb_sic_writefn
,
s
);
vpb_sic_writefn
,
s
);
...
@@ -161,8 +164,10 @@ static void versatile_init(ram_addr_t ram_size,
...
@@ -161,8 +164,10 @@ static void versatile_init(ram_addr_t ram_size,
{
{
CPUState
*
env
;
CPUState
*
env
;
ram_addr_t
ram_offset
;
ram_addr_t
ram_offset
;
qemu_irq
*
pic
;
qemu_irq
*
cpu_pic
;
qemu_irq
pic
[
32
];
qemu_irq
*
sic
;
qemu_irq
*
sic
;
DeviceState
*
dev
;
PCIBus
*
pci_bus
;
PCIBus
*
pci_bus
;
NICInfo
*
nd
;
NICInfo
*
nd
;
int
n
;
int
n
;
...
@@ -181,14 +186,18 @@ static void versatile_init(ram_addr_t ram_size,
...
@@ -181,14 +186,18 @@ static void versatile_init(ram_addr_t ram_size,
cpu_register_physical_memory
(
0
,
ram_size
,
ram_offset
|
IO_MEM_RAM
);
cpu_register_physical_memory
(
0
,
ram_size
,
ram_offset
|
IO_MEM_RAM
);
arm_sysctl_init
(
0x10000000
,
0x41007004
);
arm_sysctl_init
(
0x10000000
,
0x41007004
);
pic
=
arm_pic_init_cpu
(
env
);
cpu_pic
=
arm_pic_init_cpu
(
env
);
pic
=
pl190_init
(
0x10140000
,
pic
[
0
],
pic
[
1
]);
dev
=
sysbus_create_varargs
(
"pl190"
,
0x10140000
,
cpu_pic
[
0
],
cpu_pic
[
1
],
NULL
);
for
(
n
=
0
;
n
<
32
;
n
++
)
{
pic
[
n
]
=
qdev_get_irq_sink
(
dev
,
n
);
}
sic
=
vpb_sic_init
(
0x10003000
,
pic
,
31
);
sic
=
vpb_sic_init
(
0x10003000
,
pic
,
31
);
sysbus_create_simple
(
"pl050_keyboard"
,
0x10006000
,
sic
[
3
]);
sysbus_create_simple
(
"pl050_keyboard"
,
0x10006000
,
sic
[
3
]);
sysbus_create_simple
(
"pl050_mouse"
,
0x10007000
,
sic
[
4
]);
sysbus_create_simple
(
"pl050_mouse"
,
0x10007000
,
sic
[
4
]);
pci_bus
=
pci_vpb_init
(
sic
,
27
,
0
);
pci_bus
=
pci_vpb_init
(
sic
+
27
,
0
);
/* The Versatile PCI bridge does not provide access to PCI IO space,
/* The Versatile PCI bridge does not provide access to PCI IO space,
so many of the qemu PCI devices are not useable. */
so many of the qemu PCI devices are not useable. */
for
(
n
=
0
;
n
<
nb_nics
;
n
++
)
{
for
(
n
=
0
;
n
<
nb_nics
;
n
++
)
{
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录