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提交 97129ac8 编写于 作者: A Andreas Färber
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target-xtensa: Don't overuse CPUState 

Scripted conversion:
  sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc]
  sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NAnthony Liguori <aliguori@us.ibm.com>
上级 eb23b556
隐藏空白更改
内联 并排
Showing with 68 addition and 68 deletion
target-xtensa/cpu.h
浏览文件 @ 97129ac8
...@@ -356,27 +356,27 @@ int cpu_xtensa_exec(CPUXtensaState *s); ...@@ -356,27 +356,27 @@ int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node); void xtensa_register_core(XtensaConfigList *node);
void do_interrupt(CPUXtensaState *s); void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s); void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUState *env); void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUState *env, unsigned extint); void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUState *env, uint32_t d); void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active); void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUState *env); void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUState *env); void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUState *env); void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way); uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb, void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei); uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb, int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring); uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry(CPUState *env, bool dtlb, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUState *env, int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access); uint32_t *paddr, uint32_t *page_size, unsigned *access);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUState *new_env, uint32_t cause); void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
...@@ -392,7 +392,7 @@ static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) ...@@ -392,7 +392,7 @@ static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
} }
static inline int xtensa_get_cintlevel(const CPUState *env) static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{ {
int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
...@@ -401,7 +401,7 @@ static inline int xtensa_get_cintlevel(const CPUState *env) ...@@ -401,7 +401,7 @@ static inline int xtensa_get_cintlevel(const CPUState *env)
return level; return level;
} }
static inline int xtensa_get_ring(const CPUState *env) static inline int xtensa_get_ring(const CPUXtensaState *env)
{ {
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
...@@ -410,7 +410,7 @@ static inline int xtensa_get_ring(const CPUState *env) ...@@ -410,7 +410,7 @@ static inline int xtensa_get_ring(const CPUState *env)
} }
} }
static inline int xtensa_get_cring(const CPUState *env) static inline int xtensa_get_cring(const CPUXtensaState *env)
{ {
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
(env->sregs[PS] & PS_EXCM) == 0) { (env->sregs[PS] & PS_EXCM) == 0) {
...@@ -420,7 +420,7 @@ static inline int xtensa_get_cring(const CPUState *env) ...@@ -420,7 +420,7 @@ static inline int xtensa_get_cring(const CPUState *env)
} }
} }
static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env, static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
bool dtlb, unsigned wi, unsigned ei) bool dtlb, unsigned wi, unsigned ei)
{ {
return dtlb ? return dtlb ?
...@@ -434,7 +434,7 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env, ...@@ -434,7 +434,7 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env,
#define MMU_MODE2_SUFFIX _ring2 #define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3 #define MMU_MODE3_SUFFIX _ring3
static inline int cpu_mmu_index(CPUState *env) static inline int cpu_mmu_index(CPUXtensaState *env)
{ {
return xtensa_get_cring(env); return xtensa_get_cring(env);
} }
...@@ -445,7 +445,7 @@ static inline int cpu_mmu_index(CPUState *env) ...@@ -445,7 +445,7 @@ static inline int cpu_mmu_index(CPUState *env)
#define XTENSA_TBFLAG_DEBUG 0x10 #define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20 #define XTENSA_TBFLAG_ICOUNT 0x20
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, int *flags) target_ulong *cs_base, int *flags)
{ {
*pc = env->pc; *pc = env->pc;
...@@ -472,12 +472,12 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, ...@@ -472,12 +472,12 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
#include "cpu-all.h" #include "cpu-all.h"
#include "exec-all.h" #include "exec-all.h"
static inline int cpu_has_work(CPUState *env) static inline int cpu_has_work(CPUXtensaState *env)
{ {
return env->pending_irq_level; return env->pending_irq_level;
} }
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
{ {
env->pc = tb->pc; env->pc = tb->pc;
} }
......
target-xtensa/helper.c
浏览文件 @ 97129ac8
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include "hw/loader.h" #include "hw/loader.h"
#endif #endif
static void reset_mmu(CPUState *env); static void reset_mmu(CPUXtensaState *env);
void cpu_state_reset(CPUXtensaState *env) void cpu_state_reset(CPUXtensaState *env)
{ {
...@@ -57,7 +57,7 @@ void xtensa_register_core(XtensaConfigList *node) ...@@ -57,7 +57,7 @@ void xtensa_register_core(XtensaConfigList *node)
xtensa_cores = node; xtensa_cores = node;
} }
static uint32_t check_hw_breakpoints(CPUState *env) static uint32_t check_hw_breakpoints(CPUXtensaState *env)
{ {
unsigned i; unsigned i;
...@@ -72,7 +72,7 @@ static uint32_t check_hw_breakpoints(CPUState *env) ...@@ -72,7 +72,7 @@ static uint32_t check_hw_breakpoints(CPUState *env)
static CPUDebugExcpHandler *prev_debug_excp_handler; static CPUDebugExcpHandler *prev_debug_excp_handler;
static void breakpoint_handler(CPUState *env) static void breakpoint_handler(CPUXtensaState *env)
{ {
if (env->watchpoint_hit) { if (env->watchpoint_hit) {
if (env->watchpoint_hit->flags & BP_CPU) { if (env->watchpoint_hit->flags & BP_CPU) {
...@@ -139,7 +139,7 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) ...@@ -139,7 +139,7 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
} }
} }
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
{ {
uint32_t paddr; uint32_t paddr;
uint32_t page_size; uint32_t page_size;
...@@ -156,7 +156,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) ...@@ -156,7 +156,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return ~0; return ~0;
} }
static uint32_t relocated_vector(CPUState *env, uint32_t vector) static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{ {
if (xtensa_option_enabled(env->config, if (xtensa_option_enabled(env->config,
XTENSA_OPTION_RELOCATABLE_VECTOR)) { XTENSA_OPTION_RELOCATABLE_VECTOR)) {
...@@ -172,7 +172,7 @@ static uint32_t relocated_vector(CPUState *env, uint32_t vector) ...@@ -172,7 +172,7 @@ static uint32_t relocated_vector(CPUState *env, uint32_t vector)
* For the level-1 interrupt convert it to either user, kernel or double * For the level-1 interrupt convert it to either user, kernel or double
* exception with the 'level-1 interrupt' exception cause. * exception with the 'level-1 interrupt' exception cause.
*/ */
static void handle_interrupt(CPUState *env) static void handle_interrupt(CPUXtensaState *env)
{ {
int level = env->pending_irq_level; int level = env->pending_irq_level;
...@@ -209,7 +209,7 @@ static void handle_interrupt(CPUState *env) ...@@ -209,7 +209,7 @@ static void handle_interrupt(CPUState *env)
} }
} }
void do_interrupt(CPUState *env) void do_interrupt(CPUXtensaState *env)
{ {
if (env->exception_index == EXC_IRQ) { if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT, qemu_log_mask(CPU_LOG_INT,
...@@ -260,7 +260,7 @@ void do_interrupt(CPUState *env) ...@@ -260,7 +260,7 @@ void do_interrupt(CPUState *env)
check_interrupts(env); check_interrupts(env);
} }
static void reset_tlb_mmu_all_ways(CPUState *env, static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{ {
unsigned wi, ei; unsigned wi, ei;
...@@ -273,7 +273,7 @@ static void reset_tlb_mmu_all_ways(CPUState *env, ...@@ -273,7 +273,7 @@ static void reset_tlb_mmu_all_ways(CPUState *env,
} }
} }
static void reset_tlb_mmu_ways56(CPUState *env, static void reset_tlb_mmu_ways56(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{ {
if (!tlb->varway56) { if (!tlb->varway56) {
...@@ -320,7 +320,7 @@ static void reset_tlb_mmu_ways56(CPUState *env, ...@@ -320,7 +320,7 @@ static void reset_tlb_mmu_ways56(CPUState *env,
} }
} }
static void reset_tlb_region_way0(CPUState *env, static void reset_tlb_region_way0(CPUXtensaState *env,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{ {
unsigned ei; unsigned ei;
...@@ -334,7 +334,7 @@ static void reset_tlb_region_way0(CPUState *env, ...@@ -334,7 +334,7 @@ static void reset_tlb_region_way0(CPUState *env,
} }
} }
static void reset_mmu(CPUState *env) static void reset_mmu(CPUXtensaState *env)
{ {
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201; env->sregs[RASID] = 0x04030201;
...@@ -351,7 +351,7 @@ static void reset_mmu(CPUState *env) ...@@ -351,7 +351,7 @@ static void reset_mmu(CPUState *env)
} }
} }
static unsigned get_ring(const CPUState *env, uint8_t asid) static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
{ {
unsigned i; unsigned i;
for (i = 0; i < 4; ++i) { for (i = 0; i < 4; ++i) {
...@@ -371,7 +371,7 @@ static unsigned get_ring(const CPUState *env, uint8_t asid) ...@@ -371,7 +371,7 @@ static unsigned get_ring(const CPUState *env, uint8_t asid)
* \param pring: [out] access ring * \param pring: [out] access ring
* \return 0 if ok, exception cause code otherwise * \return 0 if ok, exception cause code otherwise
*/ */
int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb, int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring) uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{ {
const xtensa_tlb *tlb = dtlb ? const xtensa_tlb *tlb = dtlb ?
...@@ -458,10 +458,10 @@ static bool is_access_granted(unsigned access, int is_write) ...@@ -458,10 +458,10 @@ static bool is_access_granted(unsigned access, int is_write)
} }
} }
static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb, static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
uint32_t *wi, uint32_t *ei, uint8_t *ring); uint32_t *wi, uint32_t *ei, uint8_t *ring);
static int get_physical_addr_mmu(CPUState *env, static int get_physical_addr_mmu(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access) uint32_t *paddr, uint32_t *page_size, unsigned *access)
{ {
...@@ -504,7 +504,7 @@ static int get_physical_addr_mmu(CPUState *env, ...@@ -504,7 +504,7 @@ static int get_physical_addr_mmu(CPUState *env,
return 0; return 0;
} }
static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb, static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
uint32_t *wi, uint32_t *ei, uint8_t *ring) uint32_t *wi, uint32_t *ei, uint8_t *ring)
{ {
uint32_t paddr; uint32_t paddr;
...@@ -532,7 +532,7 @@ static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb, ...@@ -532,7 +532,7 @@ static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
return ret; return ret;
} }
static int get_physical_addr_region(CPUState *env, static int get_physical_addr_region(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access) uint32_t *paddr, uint32_t *page_size, unsigned *access)
{ {
...@@ -563,7 +563,7 @@ static int get_physical_addr_region(CPUState *env, ...@@ -563,7 +563,7 @@ static int get_physical_addr_region(CPUState *env,
* *
* \return 0 if ok, exception cause code otherwise * \return 0 if ok, exception cause code otherwise
*/ */
int xtensa_get_physical_addr(CPUState *env, int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access) uint32_t *paddr, uint32_t *page_size, unsigned *access)
{ {
...@@ -584,7 +584,7 @@ int xtensa_get_physical_addr(CPUState *env, ...@@ -584,7 +584,7 @@ int xtensa_get_physical_addr(CPUState *env,
} }
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
CPUState *env, bool dtlb) CPUXtensaState *env, bool dtlb)
{ {
unsigned wi, ei; unsigned wi, ei;
const xtensa_tlb *conf = const xtensa_tlb *conf =
...@@ -634,7 +634,7 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, ...@@ -634,7 +634,7 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
} }
} }
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env) void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
{ {
if (xtensa_option_bits_enabled(env->config, if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
......
target-xtensa/op_helper.c
浏览文件 @ 97129ac8
...@@ -70,10 +70,10 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user, ...@@ -70,10 +70,10 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
} }
} }
void tlb_fill(CPUState *env1, target_ulong vaddr, int is_write, int mmu_idx, void tlb_fill(CPUXtensaState *env1, target_ulong vaddr, int is_write, int mmu_idx,
void *retaddr) void *retaddr)
{ {
CPUState *saved_env = env; CPUXtensaState *saved_env = env;
env = env1; env = env1;
{ {
...@@ -134,7 +134,7 @@ void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr) ...@@ -134,7 +134,7 @@ void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
HELPER(exception_cause)(pc, cause); HELPER(exception_cause)(pc, cause);
} }
void debug_exception_env(CPUState *new_env, uint32_t cause) void debug_exception_env(CPUXtensaState *new_env, uint32_t cause)
{ {
if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) { if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) {
env = new_env; env = new_env;
...@@ -168,7 +168,7 @@ uint32_t HELPER(nsau)(uint32_t v) ...@@ -168,7 +168,7 @@ uint32_t HELPER(nsau)(uint32_t v)
return v ? clz32(v) : 32; return v ? clz32(v) : 32;
} }
static void copy_window_from_phys(CPUState *env, static void copy_window_from_phys(CPUXtensaState *env,
uint32_t window, uint32_t phys, uint32_t n) uint32_t window, uint32_t phys, uint32_t n)
{ {
assert(phys < env->config->nareg); assert(phys < env->config->nareg);
...@@ -184,7 +184,7 @@ static void copy_window_from_phys(CPUState *env, ...@@ -184,7 +184,7 @@ static void copy_window_from_phys(CPUState *env,
} }
} }
static void copy_phys_from_window(CPUState *env, static void copy_phys_from_window(CPUXtensaState *env,
uint32_t phys, uint32_t window, uint32_t n) uint32_t phys, uint32_t window, uint32_t n)
{ {
assert(phys < env->config->nareg); assert(phys < env->config->nareg);
...@@ -201,22 +201,22 @@ static void copy_phys_from_window(CPUState *env, ...@@ -201,22 +201,22 @@ static void copy_phys_from_window(CPUState *env,
} }
static inline unsigned windowbase_bound(unsigned a, const CPUState *env) static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
{ {
return a & (env->config->nareg / 4 - 1); return a & (env->config->nareg / 4 - 1);
} }
static inline unsigned windowstart_bit(unsigned a, const CPUState *env) static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
{ {
return 1 << windowbase_bound(a, env); return 1 << windowbase_bound(a, env);
} }
void xtensa_sync_window_from_phys(CPUState *env) void xtensa_sync_window_from_phys(CPUXtensaState *env)
{ {
copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
} }
void xtensa_sync_phys_from_window(CPUState *env) void xtensa_sync_phys_from_window(CPUXtensaState *env)
{ {
copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
} }
...@@ -409,7 +409,7 @@ void HELPER(advance_ccount)(uint32_t d) ...@@ -409,7 +409,7 @@ void HELPER(advance_ccount)(uint32_t d)
xtensa_advance_ccount(env, d); xtensa_advance_ccount(env, d);
} }
void HELPER(check_interrupts)(CPUState *env) void HELPER(check_interrupts)(CPUXtensaState *env)
{ {
check_interrupts(env); check_interrupts(env);
} }
...@@ -423,7 +423,7 @@ void HELPER(wsr_rasid)(uint32_t v) ...@@ -423,7 +423,7 @@ void HELPER(wsr_rasid)(uint32_t v)
} }
} }
static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way) static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
{ {
uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
...@@ -445,7 +445,7 @@ static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way) ...@@ -445,7 +445,7 @@ static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way)
/*! /*!
* Get bit mask for the virtual address bits translated by the TLB way * Get bit mask for the virtual address bits translated by the TLB way
*/ */
uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way) uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{ {
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
bool varway56 = dtlb ? bool varway56 = dtlb ?
...@@ -482,7 +482,7 @@ uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way) ...@@ -482,7 +482,7 @@ uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way)
* Get bit mask for the 'VPN without index' field. * Get bit mask for the 'VPN without index' field.
* See ISA, 4.6.5.6, data format for RxTLB0 * See ISA, 4.6.5.6, data format for RxTLB0
*/ */
static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way) static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{ {
if (way < 4) { if (way < 4) {
bool is32 = (dtlb ? bool is32 = (dtlb ?
...@@ -511,7 +511,7 @@ static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way) ...@@ -511,7 +511,7 @@ static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way)
* Split virtual address into VPN (with index) and entry index * Split virtual address into VPN (with index) and entry index
* for the given TLB way * for the given TLB way
*/ */
void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb, void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei) uint32_t *vpn, uint32_t wi, uint32_t *ei)
{ {
bool varway56 = dtlb ? bool varway56 = dtlb ?
...@@ -647,7 +647,7 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb) ...@@ -647,7 +647,7 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
} }
} }
void xtensa_tlb_set_entry(CPUState *env, bool dtlb, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{ {
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
......
target-xtensa/translate.c
浏览文件 @ 97129ac8
...@@ -159,18 +159,18 @@ void xtensa_translate_init(void) ...@@ -159,18 +159,18 @@ void xtensa_translate_init(void)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, pc), "pc"); offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, regs[i]), offsetof(CPUXtensaState, regs[i]),
regnames[i]); regnames[i]);
} }
for (i = 0; i < 256; ++i) { for (i = 0; i < 256; ++i) {
if (sregnames[i]) { if (sregnames[i]) {
cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, sregs[i]), offsetof(CPUXtensaState, sregs[i]),
sregnames[i]); sregnames[i]);
} }
} }
...@@ -178,7 +178,7 @@ void xtensa_translate_init(void) ...@@ -178,7 +178,7 @@ void xtensa_translate_init(void)
for (i = 0; i < 256; ++i) { for (i = 0; i < 256; ++i) {
if (uregnames[i]) { if (uregnames[i]) {
cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0, cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, uregs[i]), offsetof(CPUXtensaState, uregs[i]),
uregnames[i]); uregnames[i]);
} }
} }
...@@ -2493,7 +2493,7 @@ invalid_opcode: ...@@ -2493,7 +2493,7 @@ invalid_opcode:
#undef HAS_OPTION #undef HAS_OPTION
} }
static void check_breakpoint(CPUState *env, DisasContext *dc) static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
{ {
CPUBreakpoint *bp; CPUBreakpoint *bp;
...@@ -2508,7 +2508,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc) ...@@ -2508,7 +2508,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
} }
} }
static void gen_ibreak_check(CPUState *env, DisasContext *dc) static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
{ {
unsigned i; unsigned i;
...@@ -2522,7 +2522,7 @@ static void gen_ibreak_check(CPUState *env, DisasContext *dc) ...@@ -2522,7 +2522,7 @@ static void gen_ibreak_check(CPUState *env, DisasContext *dc)
} }
static void gen_intermediate_code_internal( static void gen_intermediate_code_internal(
CPUState *env, TranslationBlock *tb, int search_pc) CPUXtensaState *env, TranslationBlock *tb, int search_pc)
{ {
DisasContext dc; DisasContext dc;
int insn_count = 0; int insn_count = 0;
...@@ -2644,17 +2644,17 @@ static void gen_intermediate_code_internal( ...@@ -2644,17 +2644,17 @@ static void gen_intermediate_code_internal(
} }
} }
void gen_intermediate_code(CPUState *env, TranslationBlock *tb) void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 0); gen_intermediate_code_internal(env, tb, 0);
} }
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 1); gen_intermediate_code_internal(env, tb, 1);
} }
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
int flags) int flags)
{ {
int i, j; int i, j;
...@@ -2692,7 +2692,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, ...@@ -2692,7 +2692,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
} }
} }
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
{ {
env->pc = gen_opc_pc[pc_pos]; env->pc = gen_opc_pc[pc_pos];
} }
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