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提交 923617a3 编写于 作者: T ths
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Improved debug output for the MIPS opcode decoder. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2801 c046a42c-6fe2-441c-8c8c-71466251a162
上级 4759513b
隐藏空白更改
内联 并排
Showing with 77 addition and 85 deletion
target-mips/translate.c
浏览文件 @ 923617a3
......@@ -540,7 +540,7 @@ enum {
BS_EXCP = 3, /* We reached an exception condition */
};
#if defined MIPS_DEBUG_DISAS
#ifdef MIPS_DEBUG_DISAS
#define MIPS_DEBUG(fmt, args...) \
do { \
if (loglevel & CPU_LOG_TB_IN_ASM) { \
......@@ -710,7 +710,7 @@ OP_ST_TABLE(uxc1);
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
int base, int16_t offset)
{
const char *opn = "unk";
const char *opn = "ldst";
if (base == 0) {
GEN_LOAD_IMM_TN(T0, offset);
......@@ -849,7 +849,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
opn = "sc";
break;
default:
MIPS_INVAL("load/store");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -860,7 +860,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
int base, int16_t offset)
{
const char *opn = "unk";
const char *opn = "flt_ldst";
if (base == 0) {
GEN_LOAD_IMM_TN(T0, offset);
......@@ -896,7 +896,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
opn = "sdc1";
break;
default:
MIPS_INVAL("float load/store");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -908,7 +908,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
int rs, int16_t imm)
{
uint32_t uimm;
const char *opn = "unk";
const char *opn = "imm arith";
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
/* if no destination, treat it as a NOP
......@@ -1073,7 +1073,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
break;
#endif
default:
MIPS_INVAL("imm arith");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1085,7 +1085,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
static void gen_arith (DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "unk";
const char *opn = "arith";
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
&& opc != OPC_DADD && opc != OPC_DSUB) {
......@@ -1223,7 +1223,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
break;
#endif
default:
MIPS_INVAL("arith");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1235,7 +1235,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
/* Arithmetic on HI/LO registers */
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
{
const char *opn = "unk";
const char *opn = "hilo";
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as a NOP */
......@@ -1264,7 +1264,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
opn = "mtlo";
break;
default:
MIPS_INVAL("HILO");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1274,7 +1274,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
static void gen_muldiv (DisasContext *ctx, uint32_t opc,
int rs, int rt)
{
const char *opn = "unk";
const char *opn = "mul/div";
GEN_LOAD_REG_TN(T0, rs);
GEN_LOAD_REG_TN(T1, rt);
......@@ -1330,7 +1330,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
opn = "msubu";
break;
default:
MIPS_INVAL("mul/div");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1340,7 +1340,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
static void gen_cl (DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
const char *opn = "unk";
const char *opn = "CLx";
if (rd == 0) {
/* Treat as a NOP */
MIPS_DEBUG("NOP");
......@@ -1367,7 +1367,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
break;
#endif
default:
MIPS_INVAL("CLx");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1431,7 +1431,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
/* Never trap: treat as NOP */
return;
default:
MIPS_INVAL("TRAP");
MIPS_INVAL("trap");
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1462,7 +1462,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
gen_op_ne();
break;
default:
MIPS_INVAL("TRAP");
MIPS_INVAL("trap");
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1499,12 +1499,13 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
int bcond = 0;
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile,
"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
ctx->pc);
}
MIPS_INVAL("branch/jump in bdelay slot");
#endif
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1553,6 +1554,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (offset != 0 && offset != 16) {
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
others are reserved. */
MIPS_INVAL("jump hint");
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -1610,12 +1612,12 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
return;
case OPC_J:
ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("j %08x", btarget);
MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
break;
case OPC_JAL:
blink = 31;
ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("jal %08x", btarget);
MIPS_DEBUG("jal " TARGET_FMT_lx, btarget);
break;
case OPC_JR:
ctx->hflags |= MIPS_HFLAG_BR;
......@@ -1635,70 +1637,70 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_BEQ:
gen_op_eq();
MIPS_DEBUG("beq %s, %s, %08x",
MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
regnames[rs], regnames[rt], btarget);
goto not_likely;
case OPC_BEQL:
gen_op_eq();
MIPS_DEBUG("beql %s, %s, %08x",
MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
regnames[rs], regnames[rt], btarget);
goto likely;
case OPC_BNE:
gen_op_ne();
MIPS_DEBUG("bne %s, %s, %08x",
MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
regnames[rs], regnames[rt], btarget);
goto not_likely;
case OPC_BNEL:
gen_op_ne();
MIPS_DEBUG("bnel %s, %s, %08x",
MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
regnames[rs], regnames[rt], btarget);
goto likely;
case OPC_BGEZ:
gen_op_gez();
MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto not_likely;
case OPC_BGEZL:
gen_op_gez();
MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto likely;
case OPC_BGEZAL:
gen_op_gez();
MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
blink = 31;
goto not_likely;
case OPC_BGEZALL:
gen_op_gez();
blink = 31;
MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto likely;
case OPC_BGTZ:
gen_op_gtz();
MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto not_likely;
case OPC_BGTZL:
gen_op_gtz();
MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto likely;
case OPC_BLEZ:
gen_op_lez();
MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto not_likely;
case OPC_BLEZL:
gen_op_lez();
MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto likely;
case OPC_BLTZ:
gen_op_ltz();
MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto not_likely;
case OPC_BLTZL:
gen_op_ltz();
MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
goto likely;
case OPC_BLTZAL:
gen_op_ltz();
blink = 31;
MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
gen_op_set_bcond();
......@@ -1706,7 +1708,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
case OPC_BLTZALL:
gen_op_ltz();
blink = 31;
MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
likely:
ctx->hflags |= MIPS_HFLAG_BL;
gen_op_set_bcond();
......@@ -1718,7 +1720,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
return;
}
}
MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
blink, ctx->hflags, btarget);
ctx->btarget = btarget;
if (blink > 0) {
......@@ -4221,6 +4223,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
case OPC_DERET:
opn = "deret";
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
} else {
save_cpu_state(ctx, 0);
......@@ -4238,11 +4241,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
ctx->bstate = BS_EXCP;
break;
default:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
((ctx->opcode >> 16) & 0x1F));
}
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -4254,25 +4253,26 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
int32_t cc, int32_t offset)
{
target_ulong btarget;
const char *opn = "cp1 cond branch";
btarget = ctx->pc + 4 + offset;
switch (op) {
case OPC_BC1F:
gen_op_bc1f(cc);
MIPS_DEBUG("bc1f " TARGET_FMT_lx, btarget);
opn = "bc1f";
goto not_likely;
case OPC_BC1FL:
gen_op_bc1f(cc);
MIPS_DEBUG("bc1fl " TARGET_FMT_lx, btarget);
opn = "bc1fl";
goto likely;
case OPC_BC1T:
gen_op_bc1t(cc);
MIPS_DEBUG("bc1t " TARGET_FMT_lx, btarget);
opn = "bc1t";
goto not_likely;
case OPC_BC1TL:
gen_op_bc1t(cc);
MIPS_DEBUG("bc1tl " TARGET_FMT_lx, btarget);
opn = "bc1tl";
likely:
ctx->hflags |= MIPS_HFLAG_BL;
gen_op_set_bcond();
......@@ -4280,34 +4280,31 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
break;
case OPC_BC1FANY2:
gen_op_bc1fany2(cc);
MIPS_DEBUG("bc1fany2 " TARGET_FMT_lx, btarget);
opn = "bc1fany2";
goto not_likely;
case OPC_BC1TANY2:
gen_op_bc1tany2(cc);
MIPS_DEBUG("bc1tany2 " TARGET_FMT_lx, btarget);
opn = "bc1tany2";
goto not_likely;
case OPC_BC1FANY4:
gen_op_bc1fany4(cc);
MIPS_DEBUG("bc1fany4 " TARGET_FMT_lx, btarget);
opn = "bc1fany4";
goto not_likely;
case OPC_BC1TANY4:
gen_op_bc1tany4(cc);
MIPS_DEBUG("bc1tany4 " TARGET_FMT_lx, btarget);
opn = "bc1tany4";
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
gen_op_set_bcond();
break;
default:
MIPS_INVAL("cp1 branch");
MIPS_INVAL(opn);
generate_exception (ctx, EXCP_RI);
return;
}
MIPS_DEBUG("enter ds: cond %02x target " TARGET_FMT_lx,
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
return;
}
/* Coprocessor 1 (FPU) */
......@@ -4325,18 +4322,19 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
* FIXME: This is broken for R2, it needs to be checked at runtime, not
* at translation time.
*/
#define CHECK_FR(ctx, freg) do { \
#define CHECK_FR(ctx, freg) do { \
if (!((ctx)->CP0_Status & (1 << CP0St_FR)) && ((freg) & 1)) { \
generate_exception (ctx, EXCP_RI); \
return; \
} \
MIPS_INVAL("FPU mode"); \
generate_exception (ctx, EXCP_RI); \
return; \
} \
} while(0)
#define FOP(func, fmt) (((fmt) << 21) | (func))
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
{
const char *opn = "unk";
const char *opn = "cp1 move";
switch (opc) {
case OPC_MFC1:
......@@ -4390,11 +4388,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
opn = "mthc1";
break;
default:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
((ctx->opcode >> 16) & 0x1F));
}
MIPS_INVAL(opn);
generate_exception (ctx, EXCP_RI);
return;
}
......@@ -4440,7 +4434,7 @@ GEN_MOVCF(ps);
static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
int fs, int fd, int cc)
{
const char *opn = "unk";
const char *opn = "farith";
const char *condnames[] = {
"c.f",
"c.un",
......@@ -5041,11 +5035,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
opn = condnames[func-48];
break;
default:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
((ctx->opcode >> 16) & 0x1F));
}
MIPS_INVAL(opn);
generate_exception (ctx, EXCP_RI);
return;
}
......@@ -5059,7 +5049,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
int base, int index)
{
const char *opn = "unk";
const char *opn = "extended float load/store";
GEN_LOAD_REG_TN(T0, base);
GEN_LOAD_REG_TN(T1, index);
......@@ -5098,7 +5088,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
opn = "suxc1";
break;
default:
MIPS_INVAL("extended float load/store");
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
......@@ -5108,7 +5098,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
int fr, int fs, int ft)
{
const char *opn = "unk";
const char *opn = "flt3_arith";
/* All of those work only on 64bit FPUs. */
CHECK_FR(ctx, fd | fr | fs | ft);
......@@ -5173,11 +5163,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
generate_exception (ctx, EXCP_RI);
opn = "nmsub.ps";
break;
default:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Invalid extended FP arith function: %08x %03x %03x\n",
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F);
}
default:
MIPS_INVAL(opn);
generate_exception (ctx, EXCP_RI);
return;
}
......@@ -5459,7 +5446,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
/* treat as noop */
break;
default: /* Invalid */
MIPS_INVAL("REGIMM");
MIPS_INVAL("regimm");
generate_exception(ctx, EXCP_RI);
break;
}
......@@ -5494,7 +5481,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
ctx->bstate = BS_STOP;
break;
default: /* Invalid */
MIPS_INVAL("MFMC0");
MIPS_INVAL("mfmc0");
generate_exception(ctx, EXCP_RI);
break;
}
......@@ -5506,10 +5493,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
/* Shadow registers not implemented. */
GEN_LOAD_REG_TN(T0, rt);
GEN_STORE_TN_REG(rd, T0);
} else
} else {
MIPS_INVAL("shadow register move");
generate_exception(ctx, EXCP_RI);
}
break;
default:
MIPS_INVAL("cp0");
generate_exception(ctx, EXCP_RI);
break;
}
......@@ -5539,7 +5529,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
/* Treat as a noop */
break;
/* Floating point. */
/* Floating point (COP1). */
case OPC_LWC1:
case OPC_LDC1:
case OPC_SWC1:
......@@ -5584,6 +5574,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
(imm >> 8) & 0x7);
break;
default:
MIPS_INVAL("cp1");
generate_exception (ctx, EXCP_RI);
break;
}
......@@ -5635,6 +5626,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
MIPS_INVAL("cp3");
generate_exception (ctx, EXCP_RI);
break;
}
......@@ -5667,7 +5659,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
/* MDMX: Not implemented. */
#endif
default: /* Invalid */
MIPS_INVAL("");
MIPS_INVAL("major opcode");
generate_exception(ctx, EXCP_RI);
break;
}
......@@ -5764,7 +5756,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
#if defined MIPS_DEBUG_DISAS
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "\ntb %p super %d cond %04x\n",
tb, ctx.mem_idx, ctx.hflags);
......
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