Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
qemu
提交
8afaf050
Q
qemu
项目概览
openeuler
/
qemu
通知
10
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
Q
qemu
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
8afaf050
编写于
12月 17, 2018
作者:
R
Richard Henderson
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
tcg: Add opcodes for vector saturated arithmetic
Signed-off-by:
N
Richard Henderson
<
richard.henderson@linaro.org
>
上级
5d6acdd4
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
119 addition
and
24 deletion
+119
-24
tcg/README
tcg/README
+9
-0
tcg/aarch64/tcg-target.h
tcg/aarch64/tcg-target.h
+1
-0
tcg/i386/tcg-target.h
tcg/i386/tcg-target.h
+1
-0
tcg/tcg-op-gvec.c
tcg/tcg-op-gvec.c
+64
-20
tcg/tcg-op-vec.c
tcg/tcg-op-vec.c
+30
-4
tcg/tcg-op.h
tcg/tcg-op.h
+4
-0
tcg/tcg-opc.h
tcg/tcg-opc.h
+4
-0
tcg/tcg.c
tcg/tcg.c
+5
-0
tcg/tcg.h
tcg/tcg.h
+1
-0
未找到文件。
tcg/README
浏览文件 @
8afaf050
...
...
@@ -554,6 +554,15 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, v0 = -v1.
* ssadd_vec:
* sssub_vec:
* usadd_vec:
* ussub_vec:
Signed and unsigned saturating addition and subtraction. If the true
result is not representable within the element type, the element is
set to the minimum or maximum value for the type.
* and_vec v0, v1, v2
* or_vec v0, v1, v2
* xor_vec v0, v1, v2
...
...
tcg/aarch64/tcg-target.h
浏览文件 @
8afaf050
...
...
@@ -135,6 +135,7 @@ typedef enum {
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
...
...
tcg/i386/tcg-target.h
浏览文件 @
8afaf050
...
...
@@ -185,6 +185,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
...
...
tcg/tcg-op-gvec.c
浏览文件 @
8afaf050
...
...
@@ -1678,10 +1678,22 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t
bofs
,
uint32_t
oprsz
,
uint32_t
maxsz
)
{
static
const
GVecGen3
g
[
4
]
=
{
{
.
fno
=
gen_helper_gvec_ssadd8
,
.
vece
=
MO_8
},
{
.
fno
=
gen_helper_gvec_ssadd16
,
.
vece
=
MO_16
},
{
.
fno
=
gen_helper_gvec_ssadd32
,
.
vece
=
MO_32
},
{
.
fno
=
gen_helper_gvec_ssadd64
,
.
vece
=
MO_64
}
{
.
fniv
=
tcg_gen_ssadd_vec
,
.
fno
=
gen_helper_gvec_ssadd8
,
.
opc
=
INDEX_op_ssadd_vec
,
.
vece
=
MO_8
},
{
.
fniv
=
tcg_gen_ssadd_vec
,
.
fno
=
gen_helper_gvec_ssadd16
,
.
opc
=
INDEX_op_ssadd_vec
,
.
vece
=
MO_16
},
{
.
fniv
=
tcg_gen_ssadd_vec
,
.
fno
=
gen_helper_gvec_ssadd32
,
.
opc
=
INDEX_op_ssadd_vec
,
.
vece
=
MO_32
},
{
.
fniv
=
tcg_gen_ssadd_vec
,
.
fno
=
gen_helper_gvec_ssadd64
,
.
opc
=
INDEX_op_ssadd_vec
,
.
vece
=
MO_64
},
};
tcg_debug_assert
(
vece
<=
MO_64
);
tcg_gen_gvec_3
(
dofs
,
aofs
,
bofs
,
oprsz
,
maxsz
,
&
g
[
vece
]);
...
...
@@ -1691,16 +1703,28 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t
bofs
,
uint32_t
oprsz
,
uint32_t
maxsz
)
{
static
const
GVecGen3
g
[
4
]
=
{
{
.
fno
=
gen_helper_gvec_sssub8
,
.
vece
=
MO_8
},
{
.
fno
=
gen_helper_gvec_sssub16
,
.
vece
=
MO_16
},
{
.
fno
=
gen_helper_gvec_sssub32
,
.
vece
=
MO_32
},
{
.
fno
=
gen_helper_gvec_sssub64
,
.
vece
=
MO_64
}
{
.
fniv
=
tcg_gen_sssub_vec
,
.
fno
=
gen_helper_gvec_sssub8
,
.
opc
=
INDEX_op_sssub_vec
,
.
vece
=
MO_8
},
{
.
fniv
=
tcg_gen_sssub_vec
,
.
fno
=
gen_helper_gvec_sssub16
,
.
opc
=
INDEX_op_sssub_vec
,
.
vece
=
MO_16
},
{
.
fniv
=
tcg_gen_sssub_vec
,
.
fno
=
gen_helper_gvec_sssub32
,
.
opc
=
INDEX_op_sssub_vec
,
.
vece
=
MO_32
},
{
.
fniv
=
tcg_gen_sssub_vec
,
.
fno
=
gen_helper_gvec_sssub64
,
.
opc
=
INDEX_op_sssub_vec
,
.
vece
=
MO_64
},
};
tcg_debug_assert
(
vece
<=
MO_64
);
tcg_gen_gvec_3
(
dofs
,
aofs
,
bofs
,
oprsz
,
maxsz
,
&
g
[
vece
]);
}
static
void
tcg_gen_
vec_usadd32
_i32
(
TCGv_i32
d
,
TCGv_i32
a
,
TCGv_i32
b
)
static
void
tcg_gen_
usadd
_i32
(
TCGv_i32
d
,
TCGv_i32
a
,
TCGv_i32
b
)
{
TCGv_i32
max
=
tcg_const_i32
(
-
1
);
tcg_gen_add_i32
(
d
,
a
,
b
);
...
...
@@ -1708,7 +1732,7 @@ static void tcg_gen_vec_usadd32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_temp_free_i32
(
max
);
}
static
void
tcg_gen_
vec_usadd32
_i64
(
TCGv_i64
d
,
TCGv_i64
a
,
TCGv_i64
b
)
static
void
tcg_gen_
usadd
_i64
(
TCGv_i64
d
,
TCGv_i64
a
,
TCGv_i64
b
)
{
TCGv_i64
max
=
tcg_const_i64
(
-
1
);
tcg_gen_add_i64
(
d
,
a
,
b
);
...
...
@@ -1720,20 +1744,30 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t
bofs
,
uint32_t
oprsz
,
uint32_t
maxsz
)
{
static
const
GVecGen3
g
[
4
]
=
{
{
.
fno
=
gen_helper_gvec_usadd8
,
.
vece
=
MO_8
},
{
.
fno
=
gen_helper_gvec_usadd16
,
.
vece
=
MO_16
},
{
.
fni4
=
tcg_gen_vec_usadd32_i32
,
{
.
fniv
=
tcg_gen_usadd_vec
,
.
fno
=
gen_helper_gvec_usadd8
,
.
opc
=
INDEX_op_usadd_vec
,
.
vece
=
MO_8
},
{
.
fniv
=
tcg_gen_usadd_vec
,
.
fno
=
gen_helper_gvec_usadd16
,
.
opc
=
INDEX_op_usadd_vec
,
.
vece
=
MO_16
},
{
.
fni4
=
tcg_gen_usadd_i32
,
.
fniv
=
tcg_gen_usadd_vec
,
.
fno
=
gen_helper_gvec_usadd32
,
.
opc
=
INDEX_op_usadd_vec
,
.
vece
=
MO_32
},
{
.
fni8
=
tcg_gen_vec_usadd32_i64
,
{
.
fni8
=
tcg_gen_usadd_i64
,
.
fniv
=
tcg_gen_usadd_vec
,
.
fno
=
gen_helper_gvec_usadd64
,
.
opc
=
INDEX_op_usadd_vec
,
.
vece
=
MO_64
}
};
tcg_debug_assert
(
vece
<=
MO_64
);
tcg_gen_gvec_3
(
dofs
,
aofs
,
bofs
,
oprsz
,
maxsz
,
&
g
[
vece
]);
}
static
void
tcg_gen_
vec_ussub32
_i32
(
TCGv_i32
d
,
TCGv_i32
a
,
TCGv_i32
b
)
static
void
tcg_gen_
ussub
_i32
(
TCGv_i32
d
,
TCGv_i32
a
,
TCGv_i32
b
)
{
TCGv_i32
min
=
tcg_const_i32
(
0
);
tcg_gen_sub_i32
(
d
,
a
,
b
);
...
...
@@ -1741,7 +1775,7 @@ static void tcg_gen_vec_ussub32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_temp_free_i32
(
min
);
}
static
void
tcg_gen_
vec_ussub32
_i64
(
TCGv_i64
d
,
TCGv_i64
a
,
TCGv_i64
b
)
static
void
tcg_gen_
ussub
_i64
(
TCGv_i64
d
,
TCGv_i64
a
,
TCGv_i64
b
)
{
TCGv_i64
min
=
tcg_const_i64
(
0
);
tcg_gen_sub_i64
(
d
,
a
,
b
);
...
...
@@ -1753,13 +1787,23 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t
bofs
,
uint32_t
oprsz
,
uint32_t
maxsz
)
{
static
const
GVecGen3
g
[
4
]
=
{
{
.
fno
=
gen_helper_gvec_ussub8
,
.
vece
=
MO_8
},
{
.
fno
=
gen_helper_gvec_ussub16
,
.
vece
=
MO_16
},
{
.
fni4
=
tcg_gen_vec_ussub32_i32
,
{
.
fniv
=
tcg_gen_ussub_vec
,
.
fno
=
gen_helper_gvec_ussub8
,
.
opc
=
INDEX_op_ussub_vec
,
.
vece
=
MO_8
},
{
.
fniv
=
tcg_gen_ussub_vec
,
.
fno
=
gen_helper_gvec_ussub16
,
.
opc
=
INDEX_op_ussub_vec
,
.
vece
=
MO_16
},
{
.
fni4
=
tcg_gen_ussub_i32
,
.
fniv
=
tcg_gen_ussub_vec
,
.
fno
=
gen_helper_gvec_ussub32
,
.
opc
=
INDEX_op_ussub_vec
,
.
vece
=
MO_32
},
{
.
fni8
=
tcg_gen_vec_ussub32_i64
,
{
.
fni8
=
tcg_gen_ussub_i64
,
.
fniv
=
tcg_gen_ussub_vec
,
.
fno
=
gen_helper_gvec_ussub64
,
.
opc
=
INDEX_op_ussub_vec
,
.
vece
=
MO_64
}
};
tcg_debug_assert
(
vece
<=
MO_64
);
...
...
tcg/tcg-op-vec.c
浏览文件 @
8afaf050
...
...
@@ -386,7 +386,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
}
}
void
tcg_gen_mul_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
static
void
do_op3
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
,
TCGOpcode
opc
)
{
TCGTemp
*
rt
=
tcgv_vec_temp
(
r
);
TCGTemp
*
at
=
tcgv_vec_temp
(
a
);
...
...
@@ -399,11 +400,36 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
tcg_debug_assert
(
at
->
base_type
>=
type
);
tcg_debug_assert
(
bt
->
base_type
>=
type
);
can
=
tcg_can_emit_vec_op
(
INDEX_op_mul_ve
c
,
type
,
vece
);
can
=
tcg_can_emit_vec_op
(
op
c
,
type
,
vece
);
if
(
can
>
0
)
{
vec_gen_3
(
INDEX_op_mul_ve
c
,
type
,
vece
,
ri
,
ai
,
bi
);
vec_gen_3
(
op
c
,
type
,
vece
,
ri
,
ai
,
bi
);
}
else
{
tcg_debug_assert
(
can
<
0
);
tcg_expand_vec_op
(
INDEX_op_mul_ve
c
,
type
,
vece
,
ri
,
ai
,
bi
);
tcg_expand_vec_op
(
op
c
,
type
,
vece
,
ri
,
ai
,
bi
);
}
}
void
tcg_gen_mul_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
{
do_op3
(
vece
,
r
,
a
,
b
,
INDEX_op_mul_vec
);
}
void
tcg_gen_ssadd_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
{
do_op3
(
vece
,
r
,
a
,
b
,
INDEX_op_ssadd_vec
);
}
void
tcg_gen_usadd_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
{
do_op3
(
vece
,
r
,
a
,
b
,
INDEX_op_usadd_vec
);
}
void
tcg_gen_sssub_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
{
do_op3
(
vece
,
r
,
a
,
b
,
INDEX_op_sssub_vec
);
}
void
tcg_gen_ussub_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
)
{
do_op3
(
vece
,
r
,
a
,
b
,
INDEX_op_ussub_vec
);
}
tcg/tcg-op.h
浏览文件 @
8afaf050
...
...
@@ -967,6 +967,10 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void
tcg_gen_eqv_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
);
void
tcg_gen_not_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
);
void
tcg_gen_neg_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
);
void
tcg_gen_ssadd_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
);
void
tcg_gen_usadd_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
);
void
tcg_gen_sssub_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
);
void
tcg_gen_ussub_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
TCGv_vec
b
);
void
tcg_gen_shli_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
int64_t
i
);
void
tcg_gen_shri_vec
(
unsigned
vece
,
TCGv_vec
r
,
TCGv_vec
a
,
int64_t
i
);
...
...
tcg/tcg-opc.h
浏览文件 @
8afaf050
...
...
@@ -222,6 +222,10 @@ DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF
(
sub_vec
,
1
,
2
,
0
,
IMPLVEC
)
DEF
(
mul_vec
,
1
,
2
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_mul_vec
))
DEF
(
neg_vec
,
1
,
1
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_neg_vec
))
DEF
(
ssadd_vec
,
1
,
2
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_sat_vec
))
DEF
(
usadd_vec
,
1
,
2
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_sat_vec
))
DEF
(
sssub_vec
,
1
,
2
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_sat_vec
))
DEF
(
ussub_vec
,
1
,
2
,
0
,
IMPLVEC
|
IMPL
(
TCG_TARGET_HAS_sat_vec
))
DEF
(
and_vec
,
1
,
2
,
0
,
IMPLVEC
)
DEF
(
or_vec
,
1
,
2
,
0
,
IMPLVEC
)
...
...
tcg/tcg.c
浏览文件 @
8afaf050
...
...
@@ -1607,6 +1607,11 @@ bool tcg_op_supported(TCGOpcode op)
case
INDEX_op_shrv_vec
:
case
INDEX_op_sarv_vec
:
return
have_vec
&&
TCG_TARGET_HAS_shv_vec
;
case
INDEX_op_ssadd_vec
:
case
INDEX_op_usadd_vec
:
case
INDEX_op_sssub_vec
:
case
INDEX_op_ussub_vec
:
return
have_vec
&&
TCG_TARGET_HAS_sat_vec
;
default:
tcg_debug_assert
(
op
>
INDEX_op_last_generic
&&
op
<
NB_OPS
);
...
...
tcg/tcg.h
浏览文件 @
8afaf050
...
...
@@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录