提交 88c5188c 编写于 作者: P Peter Maydell

target/arm: Convert VMUL to decodetree

Convert the VMUL instruction to decodetree.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
上级 8a483533
...@@ -1417,3 +1417,13 @@ static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a) ...@@ -1417,3 +1417,13 @@ static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a)
{ {
return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
} }
static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
}
static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_sp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
}
...@@ -3112,7 +3112,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) ...@@ -3112,7 +3112,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rn = VFP_SREG_N(insn); rn = VFP_SREG_N(insn);
switch (op) { switch (op) {
case 0 ... 3: case 0 ... 4:
/* Already handled by decodetree */ /* Already handled by decodetree */
return 1; return 1;
default: default:
...@@ -3298,9 +3298,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) ...@@ -3298,9 +3298,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
for (;;) { for (;;) {
/* Perform the calculation. */ /* Perform the calculation. */
switch (op) { switch (op) {
case 4: /* mul: fn * fm */
gen_vfp_mul(dp);
break;
case 5: /* nmul: -(fn * fm) */ case 5: /* nmul: -(fn * fm) */
gen_vfp_mul(dp); gen_vfp_mul(dp);
gen_vfp_neg(dp); gen_vfp_neg(dp);
......
...@@ -117,3 +117,8 @@ VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ ...@@ -117,3 +117,8 @@ VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp vm=%vm_sp vn=%vn_sp vd=%vd_sp
VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp vm=%vm_dp vn=%vn_dp vd=%vd_dp
VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp
VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
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