target-mips: fix commits 7040 and 7042

CPU state should also be saved for helpers that in fine call
cpu_unlink_tb(). Reported by Stefan Weil.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7096 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/translate.c

@@ -3697,6 +3697,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
     case 12:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_status(t0);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
@@ -3731,6 +3732,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
     case 13:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_cause(t0);
             rn = "Cause";
             break;
@@ -4861,6 +4863,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
     case 12:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_status(t0);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
@@ -4895,14 +4898,13 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
     case 13:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_cause(t0);
             rn = "Cause";
             break;
         default:
             goto die;
         }
-        /* Stop translation as we may have switched the execution mode */
-        ctx->bstate = BS_STOP;
         break;
     case 14:
         switch (sel) {
@@ -7972,6 +7974,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
                     break;
                 case OPC_DI:
                     check_insn(env, ctx, ISA_MIPS32R2);
+                    save_cpu_state(ctx, 1);
                     gen_helper_di(t0);
                     gen_store_gpr(t0, rt);
                     /* Stop translation as we may have switched the execution mode */
@@ -7979,6 +7982,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
                     break;
                 case OPC_EI:
                     check_insn(env, ctx, ISA_MIPS32R2);
+                    save_cpu_state(ctx, 1);
                     gen_helper_ei(t0);
                     gen_store_gpr(t0, rt);
                     /* Stop translation as we may have switched the execution mode */