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提交 80cabfad 编写于 作者: B bellard
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separated more devices from emulator 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@656 c046a42c-6fe2-441c-8c8c-71466251a162
上级 38ca2abc
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Makefile.target
浏览文件 @ 80cabfad
include config.mak
TARGET_PATH=$(SRC_PATH)/target-$(TARGET_ARCH)
VPATH=$(SRC_PATH):$(TARGET_PATH)
VPATH=$(SRC_PATH):$(TARGET_PATH):$(SRC_PATH)/hw
CFLAGS=-Wall -O2 -g
LDFLAGS=-g
LIBS=
......@@ -204,7 +204,8 @@ ifeq ($(ARCH),alpha)
endif
# must use static linking to avoid leaving stuff in virtual address space
VL_OBJS=vl.o block.o ide.o vga.o sb16.o dma.o oss.o fdc.o osdep.o
VL_OBJS=vl.o osdep.o block.o ide.o ne2000.o pckbd.o vga.o sb16.o dma.o oss.o \
fdc.o mc146818rtc.o serial.o i8259.o i8254.o pc.o
ifeq ($(TARGET_ARCH), ppc)
VL_OBJS+= hw.o
endif
......
hw/i8254.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU 8253/8254 interval timer emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
#define RW_STATE_LSB 0
#define RW_STATE_MSB 1
#define RW_STATE_WORD0 2
#define RW_STATE_WORD1 3
#define RW_STATE_LATCHED_WORD0 4
#define RW_STATE_LATCHED_WORD1 5
PITChannelState pit_channels[3];
static int pit_get_count(PITChannelState *s)
{
uint64_t d;
int counter;
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
switch(s->mode) {
case 0:
case 1:
case 4:
case 5:
counter = (s->count - d) & 0xffff;
break;
case 3:
/* XXX: may be incorrect for odd counts */
counter = s->count - ((2 * d) % s->count);
break;
default:
counter = s->count - (d % s->count);
break;
}
return counter;
}
/* get pit output bit */
int pit_get_out(PITChannelState *s)
{
uint64_t d;
int out;
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
switch(s->mode) {
default:
case 0:
out = (d >= s->count);
break;
case 1:
out = (d < s->count);
break;
case 2:
if ((d % s->count) == 0 && d != 0)
out = 1;
else
out = 0;
break;
case 3:
out = (d % s->count) < ((s->count + 1) >> 1);
break;
case 4:
case 5:
out = (d == s->count);
break;
}
return out;
}
/* get the number of 0 to 1 transitions we had since we call this
function */
/* XXX: maybe better to use ticks precision to avoid getting edges
twice if checks are done at very small intervals */
int pit_get_out_edges(PITChannelState *s)
{
uint64_t d1, d2;
int64_t ticks;
int ret, v;
ticks = cpu_get_ticks();
d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
PIT_FREQ, ticks_per_sec);
d2 = muldiv64(ticks - s->count_load_time,
PIT_FREQ, ticks_per_sec);
s->count_last_edge_check_time = ticks;
switch(s->mode) {
default:
case 0:
if (d1 < s->count && d2 >= s->count)
ret = 1;
else
ret = 0;
break;
case 1:
ret = 0;
break;
case 2:
d1 /= s->count;
d2 /= s->count;
ret = d2 - d1;
break;
case 3:
v = s->count - ((s->count + 1) >> 1);
d1 = (d1 + v) / s->count;
d2 = (d2 + v) / s->count;
ret = d2 - d1;
break;
case 4:
case 5:
if (d1 < s->count && d2 >= s->count)
ret = 1;
else
ret = 0;
break;
}
return ret;
}
/* val must be 0 or 1 */
void pit_set_gate(PITChannelState *s, int val)
{
switch(s->mode) {
default:
case 0:
case 4:
/* XXX: just disable/enable counting */
break;
case 1:
case 5:
if (s->gate < val) {
/* restart counting on rising edge */
s->count_load_time = cpu_get_ticks();
s->count_last_edge_check_time = s->count_load_time;
}
break;
case 2:
case 3:
if (s->gate < val) {
/* restart counting on rising edge */
s->count_load_time = cpu_get_ticks();
s->count_last_edge_check_time = s->count_load_time;
}
/* XXX: disable/enable counting */
break;
}
s->gate = val;
}
static inline void pit_load_count(PITChannelState *s, int val)
{
if (val == 0)
val = 0x10000;
s->count_load_time = cpu_get_ticks();
s->count_last_edge_check_time = s->count_load_time;
s->count = val;
if (s == &pit_channels[0] && val <= pit_min_timer_count) {
fprintf(stderr,
"\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
PIT_FREQ / pit_min_timer_count);
}
}
void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
int channel, access;
PITChannelState *s;
addr &= 3;
if (addr == 3) {
channel = val >> 6;
if (channel == 3)
return;
s = &pit_channels[channel];
access = (val >> 4) & 3;
switch(access) {
case 0:
s->latched_count = pit_get_count(s);
s->rw_state = RW_STATE_LATCHED_WORD0;
break;
default:
s->mode = (val >> 1) & 7;
s->bcd = val & 1;
s->rw_state = access - 1 + RW_STATE_LSB;
break;
}
} else {
s = &pit_channels[addr];
switch(s->rw_state) {
case RW_STATE_LSB:
pit_load_count(s, val);
break;
case RW_STATE_MSB:
pit_load_count(s, val << 8);
break;
case RW_STATE_WORD0:
case RW_STATE_WORD1:
if (s->rw_state & 1) {
pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
} else {
s->latched_count = val;
}
s->rw_state ^= 1;
break;
}
}
}
uint32_t pit_ioport_read(CPUState *env, uint32_t addr)
{
int ret, count;
PITChannelState *s;
addr &= 3;
s = &pit_channels[addr];
switch(s->rw_state) {
case RW_STATE_LSB:
case RW_STATE_MSB:
case RW_STATE_WORD0:
case RW_STATE_WORD1:
count = pit_get_count(s);
if (s->rw_state & 1)
ret = (count >> 8) & 0xff;
else
ret = count & 0xff;
if (s->rw_state & 2)
s->rw_state ^= 1;
break;
default:
case RW_STATE_LATCHED_WORD0:
case RW_STATE_LATCHED_WORD1:
if (s->rw_state & 1)
ret = s->latched_count >> 8;
else
ret = s->latched_count & 0xff;
s->rw_state ^= 1;
break;
}
return ret;
}
void pit_init(void)
{
PITChannelState *s;
int i;
for(i = 0;i < 3; i++) {
s = &pit_channels[i];
s->mode = 3;
s->gate = (i != 2);
pit_load_count(s, 0);
}
register_ioport_write(0x40, 4, pit_ioport_write, 1);
register_ioport_read(0x40, 3, pit_ioport_read, 1);
}
hw/i8259.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU 8259 interrupt controller emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
/* debug PIC */
//#define DEBUG_PIC
typedef struct PicState {
uint8_t last_irr; /* edge detection */
uint8_t irr; /* interrupt request register */
uint8_t imr; /* interrupt mask register */
uint8_t isr; /* interrupt service register */
uint8_t priority_add; /* highest irq priority */
uint8_t irq_base;
uint8_t read_reg_select;
uint8_t poll;
uint8_t special_mask;
uint8_t init_state;
uint8_t auto_eoi;
uint8_t rotate_on_auto_eoi;
uint8_t special_fully_nested_mode;
uint8_t init4; /* true if 4 byte init */
} PicState;
/* 0 is master pic, 1 is slave pic */
PicState pics[2];
int pic_irq_requested;
/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
int mask;
mask = 1 << irq;
if (level) {
if ((s->last_irr & mask) == 0)
s->irr |= mask;
s->last_irr |= mask;
} else {
s->last_irr &= ~mask;
}
}
/* return the highest priority found in mask (highest = smallest
number). Return 8 if no irq */
static inline int get_priority(PicState *s, int mask)
{
int priority;
if (mask == 0)
return 8;
priority = 0;
while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
priority++;
return priority;
}
/* return the pic wanted interrupt. return -1 if none */
static int pic_get_irq(PicState *s)
{
int mask, cur_priority, priority;
mask = s->irr & ~s->imr;
priority = get_priority(s, mask);
if (priority == 8)
return -1;
/* compute current priority. If special fully nested mode on the
master, the IRQ coming from the slave is not taken into account
for the priority computation. */
mask = s->isr;
if (s->special_fully_nested_mode && s == &pics[0])
mask &= ~(1 << 2);
cur_priority = get_priority(s, mask);
if (priority < cur_priority) {
/* higher priority found: an irq should be generated */
return (priority + s->priority_add) & 7;
} else {
return -1;
}
}
/* raise irq to CPU if necessary. must be called every time the active
irq may change */
void pic_update_irq(void)
{
int irq2, irq;
/* first look at slave pic */
irq2 = pic_get_irq(&pics[1]);
if (irq2 >= 0) {
/* if irq request by slave pic, signal master PIC */
pic_set_irq1(&pics[0], 2, 1);
pic_set_irq1(&pics[0], 2, 0);
}
/* look at requested irq */
irq = pic_get_irq(&pics[0]);
if (irq >= 0) {
if (irq == 2) {
/* from slave pic */
pic_irq_requested = 8 + irq2;
} else {
/* from master pic */
pic_irq_requested = irq;
}
#if defined(DEBUG_PIC)
{
int i;
for(i = 0; i < 2; i++) {
printf("pic%d: imr=%x irr=%x padd=%d\n",
i, pics[i].imr, pics[i].irr, pics[i].priority_add);
}
}
printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
#endif
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
}
}
#ifdef DEBUG_IRQ_LATENCY
int64_t irq_time[16];
int64_t cpu_get_ticks(void);
#endif
#if defined(DEBUG_PIC)
int irq_level[16];
#endif
void pic_set_irq(int irq, int level)
{
#if defined(DEBUG_PIC)
if (level != irq_level[irq]) {
printf("pic_set_irq: irq=%d level=%d\n", irq, level);
irq_level[irq] = level;
}
#endif
#ifdef DEBUG_IRQ_LATENCY
if (level) {
irq_time[irq] = cpu_get_ticks();
}
#endif
pic_set_irq1(&pics[irq >> 3], irq & 7, level);
pic_update_irq();
}
/* acknowledge interrupt 'irq' */
static inline void pic_intack(PicState *s, int irq)
{
if (s->auto_eoi) {
if (s->rotate_on_auto_eoi)
s->priority_add = (irq + 1) & 7;
} else {
s->isr |= (1 << irq);
}
s->irr &= ~(1 << irq);
}
int cpu_x86_get_pic_interrupt(CPUState *env)
{
int irq, irq2, intno;
/* signal the pic that the irq was acked by the CPU */
irq = pic_irq_requested;
#ifdef DEBUG_IRQ_LATENCY
printf("IRQ%d latency=%0.3fus\n",
irq,
(double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
#endif
#if defined(DEBUG_PIC)
printf("pic_interrupt: irq=%d\n", irq);
#endif
if (irq >= 8) {
irq2 = irq & 7;
pic_intack(&pics[1], irq2);
irq = 2;
intno = pics[1].irq_base + irq2;
} else {
intno = pics[0].irq_base + irq;
}
pic_intack(&pics[0], irq);
return intno;
}
void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
PicState *s;
int priority, cmd, irq;
#ifdef DEBUG_PIC
printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
#endif
s = &pics[addr >> 7];
addr &= 1;
if (addr == 0) {
if (val & 0x10) {
/* init */
memset(s, 0, sizeof(PicState));
s->init_state = 1;
s->init4 = val & 1;
if (val & 0x02)
hw_error("single mode not supported");
if (val & 0x08)
hw_error("level sensitive irq not supported");
} else if (val & 0x08) {
if (val & 0x04)
s->poll = 1;
if (val & 0x02)
s->read_reg_select = val & 1;
if (val & 0x40)
s->special_mask = (val >> 5) & 1;
} else {
cmd = val >> 5;
switch(cmd) {
case 0:
case 4:
s->rotate_on_auto_eoi = cmd >> 2;
break;
case 1: /* end of interrupt */
case 5:
priority = get_priority(s, s->isr);
if (priority != 8) {
irq = (priority + s->priority_add) & 7;
s->isr &= ~(1 << irq);
if (cmd == 5)
s->priority_add = (irq + 1) & 7;
pic_update_irq();
}
break;
case 3:
irq = val & 7;
s->isr &= ~(1 << irq);
pic_update_irq();
break;
case 6:
s->priority_add = (val + 1) & 7;
pic_update_irq();
break;
case 7:
irq = val & 7;
s->isr &= ~(1 << irq);
s->priority_add = (irq + 1) & 7;
pic_update_irq();
break;
default:
/* no operation */
break;
}
}
} else {
switch(s->init_state) {
case 0:
/* normal mode */
s->imr = val;
pic_update_irq();
break;
case 1:
s->irq_base = val & 0xf8;
s->init_state = 2;
break;
case 2:
if (s->init4) {
s->init_state = 3;
} else {
s->init_state = 0;
}
break;
case 3:
s->special_fully_nested_mode = (val >> 4) & 1;
s->auto_eoi = (val >> 1) & 1;
s->init_state = 0;
break;
}
}
}
static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
{
int ret;
ret = pic_get_irq(s);
if (ret >= 0) {
if (addr1 >> 7) {
pics[0].isr &= ~(1 << 2);
pics[0].irr &= ~(1 << 2);
}
s->irr &= ~(1 << ret);
s->isr &= ~(1 << ret);
if (addr1 >> 7 || ret != 2)
pic_update_irq();
} else {
ret = 0x07;
pic_update_irq();
}
return ret;
}
uint32_t pic_ioport_read(CPUState *env, uint32_t addr1)
{
PicState *s;
unsigned int addr;
int ret;
addr = addr1;
s = &pics[addr >> 7];
addr &= 1;
if (s->poll) {
ret = pic_poll_read(s, addr1);
s->poll = 0;
} else {
if (addr == 0) {
if (s->read_reg_select)
ret = s->isr;
else
ret = s->irr;
} else {
ret = s->imr;
}
}
#ifdef DEBUG_PIC
printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
#endif
return ret;
}
/* memory mapped interrupt status */
uint32_t pic_intack_read(CPUState *env)
{
int ret;
ret = pic_poll_read(&pics[0], 0x00);
if (ret == 2)
ret = pic_poll_read(&pics[1], 0x80) + 8;
/* Prepare for ISR read */
pics[0].read_reg_select = 1;
return ret;
}
void pic_init(void)
{
#if defined (TARGET_I386) || defined (TARGET_PPC)
register_ioport_write(0x20, 2, pic_ioport_write, 1);
register_ioport_read(0x20, 2, pic_ioport_read, 1);
register_ioport_write(0xa0, 2, pic_ioport_write, 1);
register_ioport_read(0xa0, 2, pic_ioport_read, 1);
#endif
}
hw/mc146818rtc.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU MC146818 RTC emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
//#define DEBUG_CMOS
#define RTC_SECONDS 0
#define RTC_SECONDS_ALARM 1
#define RTC_MINUTES 2
#define RTC_MINUTES_ALARM 3
#define RTC_HOURS 4
#define RTC_HOURS_ALARM 5
#define RTC_ALARM_DONT_CARE 0xC0
#define RTC_DAY_OF_WEEK 6
#define RTC_DAY_OF_MONTH 7
#define RTC_MONTH 8
#define RTC_YEAR 9
#define RTC_REG_A 10
#define RTC_REG_B 11
#define RTC_REG_C 12
#define RTC_REG_D 13
/* PC cmos mappings */
#define REG_IBM_CENTURY_BYTE 0x32
#define REG_IBM_PS2_CENTURY_BYTE 0x37
RTCState rtc_state;
static void cmos_ioport_write(CPUState *env, uint32_t addr, uint32_t data)
{
RTCState *s = &rtc_state;
if ((addr & 1) == 0) {
s->cmos_index = data & 0x7f;
} else {
#ifdef DEBUG_CMOS
printf("cmos: write index=0x%02x val=0x%02x\n",
s->cmos_index, data);
#endif
switch(addr) {
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
/* XXX: not supported */
s->cmos_data[s->cmos_index] = data;
break;
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
s->cmos_data[s->cmos_index] = data;
break;
case RTC_REG_A:
case RTC_REG_B:
s->cmos_data[s->cmos_index] = data;
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
default:
s->cmos_data[s->cmos_index] = data;
break;
}
}
}
static inline int to_bcd(int a)
{
return ((a / 10) << 4) | (a % 10);
}
static void cmos_update_time(RTCState *s)
{
struct tm *tm;
time_t ti;
ti = time(NULL);
tm = gmtime(&ti);
s->cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
s->cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
s->cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
s->cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
s->cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
s->cmos_data[REG_IBM_CENTURY_BYTE] = to_bcd((tm->tm_year / 100) + 19);
s->cmos_data[REG_IBM_PS2_CENTURY_BYTE] = s->cmos_data[REG_IBM_CENTURY_BYTE];
}
static uint32_t cmos_ioport_read(CPUState *env, uint32_t addr)
{
RTCState *s = &rtc_state;
int ret;
if ((addr & 1) == 0) {
return 0xff;
} else {
switch(s->cmos_index) {
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
case REG_IBM_CENTURY_BYTE:
case REG_IBM_PS2_CENTURY_BYTE:
cmos_update_time(s);
ret = s->cmos_data[s->cmos_index];
break;
case RTC_REG_A:
ret = s->cmos_data[s->cmos_index];
/* toggle update-in-progress bit for Linux (same hack as
plex86) */
s->cmos_data[RTC_REG_A] ^= 0x80;
break;
case RTC_REG_C:
ret = s->cmos_data[s->cmos_index];
pic_set_irq(s->irq, 0);
s->cmos_data[RTC_REG_C] = 0x00;
break;
default:
ret = s->cmos_data[s->cmos_index];
break;
}
#ifdef DEBUG_CMOS
printf("cmos: read index=0x%02x val=0x%02x\n",
s->cmos_index, ret);
#endif
return ret;
}
}
void rtc_timer(void)
{
RTCState *s = &rtc_state;
if (s->cmos_data[RTC_REG_B] & 0x50) {
pic_set_irq(s->irq, 1);
}
}
void rtc_init(int base, int irq)
{
RTCState *s = &rtc_state;
cmos_update_time(s);
s->irq = irq;
s->cmos_data[RTC_REG_A] = 0x26;
s->cmos_data[RTC_REG_B] = 0x02;
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
register_ioport_write(base, 2, cmos_ioport_write, 1);
register_ioport_read(base, 2, cmos_ioport_read, 1);
}
hw/ne2000.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU NE2000 emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
/* debug NE2000 card */
//#define DEBUG_NE2000
/***********************************************************/
/* ne2000 emulation */
#define E8390_CMD 0x00 /* The command register (for all pages) */
/* Page 0 register offsets. */
#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
#define EN0_TSR 0x04 /* Transmit status reg RD */
#define EN0_TPSR 0x04 /* Transmit starting page WR */
#define EN0_NCR 0x05 /* Number of collision reg RD */
#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
#define EN0_FIFO 0x06 /* FIFO RD */
#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
#define EN0_RSR 0x0c /* rx status reg RD */
#define EN0_RXCR 0x0c /* RX configuration reg WR */
#define EN0_TXCR 0x0d /* TX configuration reg WR */
#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
#define EN0_DCFG 0x0e /* Data configuration reg WR */
#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
#define EN0_IMR 0x0f /* Interrupt mask reg WR */
#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
#define EN1_PHYS 0x11
#define EN1_CURPAG 0x17
#define EN1_MULT 0x18
/* Register accessed at EN_CMD, the 8390 base addr. */
#define E8390_STOP 0x01 /* Stop and reset the chip */
#define E8390_START 0x02 /* Start the chip, clear reset */
#define E8390_TRANS 0x04 /* Transmit a frame */
#define E8390_RREAD 0x08 /* Remote read */
#define E8390_RWRITE 0x10 /* Remote write */
#define E8390_NODMA 0x20 /* Remote DMA */
#define E8390_PAGE0 0x00 /* Select page chip registers */
#define E8390_PAGE1 0x40 /* using the two high-order bits */
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
/* Bits in EN0_ISR - Interrupt status register */
#define ENISR_RX 0x01 /* Receiver, no error */
#define ENISR_TX 0x02 /* Transmitter, no error */
#define ENISR_RX_ERR 0x04 /* Receiver, with error */
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
#define ENISR_COUNTERS 0x20 /* Counters need emptying */
#define ENISR_RDC 0x40 /* remote dma complete */
#define ENISR_RESET 0x80 /* Reset completed */
#define ENISR_ALL 0x3f /* Interrupts we will enable */
/* Bits in received packet status byte and EN0_RSR*/
#define ENRSR_RXOK 0x01 /* Received a good packet */
#define ENRSR_CRC 0x02 /* CRC error */
#define ENRSR_FAE 0x04 /* frame alignment error */
#define ENRSR_FO 0x08 /* FIFO overrun */
#define ENRSR_MPA 0x10 /* missed pkt */
#define ENRSR_PHY 0x20 /* physical/multicast address */
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
#define ENRSR_DEF 0x80 /* deferring */
/* Transmitted packet status, EN0_TSR. */
#define ENTSR_PTX 0x01 /* Packet transmitted without error */
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
#define ENTSR_COL 0x04 /* The transmit collided at least once. */
#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
#define NE2000_MEM_SIZE 32768
typedef struct NE2000State {
uint8_t cmd;
uint32_t start;
uint32_t stop;
uint8_t boundary;
uint8_t tsr;
uint8_t tpsr;
uint16_t tcnt;
uint16_t rcnt;
uint32_t rsar;
uint8_t isr;
uint8_t dcfg;
uint8_t imr;
uint8_t phys[6]; /* mac address */
uint8_t curpag;
uint8_t mult[8]; /* multicast mask array */
int irq;
uint8_t mem[NE2000_MEM_SIZE];
} NE2000State;
static NE2000State ne2000_state;
int net_fd = -1;
static void ne2000_reset(NE2000State *s)
{
int i;
s->isr = ENISR_RESET;
s->mem[0] = 0x52;
s->mem[1] = 0x54;
s->mem[2] = 0x00;
s->mem[3] = 0x12;
s->mem[4] = 0x34;
s->mem[5] = 0x56;
s->mem[14] = 0x57;
s->mem[15] = 0x57;
/* duplicate prom data */
for(i = 15;i >= 0; i--) {
s->mem[2 * i] = s->mem[i];
s->mem[2 * i + 1] = s->mem[i];
}
}
static void ne2000_update_irq(NE2000State *s)
{
int isr;
isr = s->isr & s->imr;
if (isr)
pic_set_irq(s->irq, 1);
else
pic_set_irq(s->irq, 0);
}
/* return true if the NE2000 can receive more data */
int ne2000_can_receive(void)
{
NE2000State *s = &ne2000_state;
int avail, index, boundary;
if (s->cmd & E8390_STOP)
return 0;
index = s->curpag << 8;
boundary = s->boundary << 8;
if (index < boundary)
avail = boundary - index;
else
avail = (s->stop - s->start) - (index - boundary);
if (avail < (MAX_ETH_FRAME_SIZE + 4))
return 0;
return 1;
}
void ne2000_receive(uint8_t *buf, int size)
{
NE2000State *s = &ne2000_state;
uint8_t *p;
int total_len, next, avail, len, index;
#if defined(DEBUG_NE2000)
printf("NE2000: received len=%d\n", size);
#endif
index = s->curpag << 8;
/* 4 bytes for header */
total_len = size + 4;
/* address for next packet (4 bytes for CRC) */
next = index + ((total_len + 4 + 255) & ~0xff);
if (next >= s->stop)
next -= (s->stop - s->start);
/* prepare packet header */
p = s->mem + index;
p[0] = ENRSR_RXOK; /* receive status */
p[1] = next >> 8;
p[2] = total_len;
p[3] = total_len >> 8;
index += 4;
/* write packet data */
while (size > 0) {
avail = s->stop - index;
len = size;
if (len > avail)
len = avail;
memcpy(s->mem + index, buf, len);
buf += len;
index += len;
if (index == s->stop)
index = s->start;
size -= len;
}
s->curpag = next >> 8;
/* now we can signal we have receive something */
s->isr |= ENISR_RX;
ne2000_update_irq(s);
}
static void ne2000_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
NE2000State *s = &ne2000_state;
int offset, page;
addr &= 0xf;
#ifdef DEBUG_NE2000
printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
#endif
if (addr == E8390_CMD) {
/* control register */
s->cmd = val;
if (val & E8390_START) {
/* test specific case: zero length transfert */
if ((val & (E8390_RREAD | E8390_RWRITE)) &&
s->rcnt == 0) {
s->isr |= ENISR_RDC;
ne2000_update_irq(s);
}
if (val & E8390_TRANS) {
net_send_packet(net_fd, s->mem + (s->tpsr << 8), s->tcnt);
/* signal end of transfert */
s->tsr = ENTSR_PTX;
s->isr |= ENISR_TX;
ne2000_update_irq(s);
}
}
} else {
page = s->cmd >> 6;
offset = addr | (page << 4);
switch(offset) {
case EN0_STARTPG:
s->start = val << 8;
break;
case EN0_STOPPG:
s->stop = val << 8;
break;
case EN0_BOUNDARY:
s->boundary = val;
break;
case EN0_IMR:
s->imr = val;
ne2000_update_irq(s);
break;
case EN0_TPSR:
s->tpsr = val;
break;
case EN0_TCNTLO:
s->tcnt = (s->tcnt & 0xff00) | val;
break;
case EN0_TCNTHI:
s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
break;
case EN0_RSARLO:
s->rsar = (s->rsar & 0xff00) | val;
break;
case EN0_RSARHI:
s->rsar = (s->rsar & 0x00ff) | (val << 8);
break;
case EN0_RCNTLO:
s->rcnt = (s->rcnt & 0xff00) | val;
break;
case EN0_RCNTHI:
s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
break;
case EN0_DCFG:
s->dcfg = val;
break;
case EN0_ISR:
s->isr &= ~val;
ne2000_update_irq(s);
break;
case EN1_PHYS ... EN1_PHYS + 5:
s->phys[offset - EN1_PHYS] = val;
break;
case EN1_CURPAG:
s->curpag = val;
break;
case EN1_MULT ... EN1_MULT + 7:
s->mult[offset - EN1_MULT] = val;
break;
}
}
}
static uint32_t ne2000_ioport_read(CPUState *env, uint32_t addr)
{
NE2000State *s = &ne2000_state;
int offset, page, ret;
addr &= 0xf;
if (addr == E8390_CMD) {
ret = s->cmd;
} else {
page = s->cmd >> 6;
offset = addr | (page << 4);
switch(offset) {
case EN0_TSR:
ret = s->tsr;
break;
case EN0_BOUNDARY:
ret = s->boundary;
break;
case EN0_ISR:
ret = s->isr;
break;
case EN1_PHYS ... EN1_PHYS + 5:
ret = s->phys[offset - EN1_PHYS];
break;
case EN1_CURPAG:
ret = s->curpag;
break;
case EN1_MULT ... EN1_MULT + 7:
ret = s->mult[offset - EN1_MULT];
break;
default:
ret = 0x00;
break;
}
}
#ifdef DEBUG_NE2000
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
#endif
return ret;
}
static void ne2000_asic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
NE2000State *s = &ne2000_state;
uint8_t *p;
#ifdef DEBUG_NE2000
printf("NE2000: asic write val=0x%04x\n", val);
#endif
p = s->mem + s->rsar;
if (s->dcfg & 0x01) {
/* 16 bit access */
p[0] = val;
p[1] = val >> 8;
s->rsar += 2;
s->rcnt -= 2;
} else {
/* 8 bit access */
p[0] = val;
s->rsar++;
s->rcnt--;
}
/* wrap */
if (s->rsar == s->stop)
s->rsar = s->start;
if (s->rcnt == 0) {
/* signal end of transfert */
s->isr |= ENISR_RDC;
ne2000_update_irq(s);
}
}
static uint32_t ne2000_asic_ioport_read(CPUState *env, uint32_t addr)
{
NE2000State *s = &ne2000_state;
uint8_t *p;
int ret;
p = s->mem + s->rsar;
if (s->dcfg & 0x01) {
/* 16 bit access */
ret = p[0] | (p[1] << 8);
s->rsar += 2;
s->rcnt -= 2;
} else {
/* 8 bit access */
ret = p[0];
s->rsar++;
s->rcnt--;
}
/* wrap */
if (s->rsar == s->stop)
s->rsar = s->start;
if (s->rcnt == 0) {
/* signal end of transfert */
s->isr |= ENISR_RDC;
ne2000_update_irq(s);
}
#ifdef DEBUG_NE2000
printf("NE2000: asic read val=0x%04x\n", ret);
#endif
return ret;
}
static void ne2000_reset_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
/* nothing to do (end of reset pulse) */
}
static uint32_t ne2000_reset_ioport_read(CPUState *env, uint32_t addr)
{
NE2000State *s = &ne2000_state;
ne2000_reset(s);
return 0;
}
void ne2000_init(int base, int irq)
{
NE2000State *s = &ne2000_state;
register_ioport_write(base, 16, ne2000_ioport_write, 1);
register_ioport_read(base, 16, ne2000_ioport_read, 1);
register_ioport_write(base + 0x10, 1, ne2000_asic_ioport_write, 1);
register_ioport_read(base + 0x10, 1, ne2000_asic_ioport_read, 1);
register_ioport_write(base + 0x10, 2, ne2000_asic_ioport_write, 2);
register_ioport_read(base + 0x10, 2, ne2000_asic_ioport_read, 2);
register_ioport_write(base + 0x1f, 1, ne2000_reset_ioport_write, 1);
register_ioport_read(base + 0x1f, 1, ne2000_reset_ioport_read, 1);
s->irq = irq;
ne2000_reset(s);
}
hw/pc.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU PC System Emulator
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
#define BIOS_FILENAME "bios.bin"
#define VGABIOS_FILENAME "vgabios.bin"
#define LINUX_BOOT_FILENAME "linux_boot.bin"
#define KERNEL_LOAD_ADDR 0x00100000
#define INITRD_LOAD_ADDR 0x00400000
#define KERNEL_PARAMS_ADDR 0x00090000
#define KERNEL_CMDLINE_ADDR 0x00099000
int speaker_data_on;
int dummy_refresh_clock;
static void ioport80_write(CPUState *env, uint32_t addr, uint32_t data)
{
}
#define REG_EQUIPMENT_BYTE 0x14
static void cmos_init(int ram_size, int boot_device)
{
RTCState *s = &rtc_state;
int val;
/* various important CMOS locations needed by PC/Bochs bios */
s->cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
/* memory size */
val = (ram_size / 1024) - 1024;
if (val > 65535)
val = 65535;
s->cmos_data[0x17] = val;
s->cmos_data[0x18] = val >> 8;
s->cmos_data[0x30] = val;
s->cmos_data[0x31] = val >> 8;
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
if (val > 65535)
val = 65535;
s->cmos_data[0x34] = val;
s->cmos_data[0x35] = val >> 8;
switch(boot_device) {
case 'a':
case 'b':
s->cmos_data[0x3d] = 0x01; /* floppy boot */
break;
default:
case 'c':
s->cmos_data[0x3d] = 0x02; /* hard drive boot */
break;
case 'd':
s->cmos_data[0x3d] = 0x03; /* CD-ROM boot */
break;
}
}
void cmos_register_fd (uint8_t fd0, uint8_t fd1)
{
RTCState *s = &rtc_state;
int nb = 0;
s->cmos_data[0x10] = 0;
switch (fd0) {
case 0:
/* 1.44 Mb 3"5 drive */
s->cmos_data[0x10] |= 0x40;
break;
case 1:
/* 2.88 Mb 3"5 drive */
s->cmos_data[0x10] |= 0x60;
break;
case 2:
/* 1.2 Mb 5"5 drive */
s->cmos_data[0x10] |= 0x20;
break;
}
switch (fd1) {
case 0:
/* 1.44 Mb 3"5 drive */
s->cmos_data[0x10] |= 0x04;
break;
case 1:
/* 2.88 Mb 3"5 drive */
s->cmos_data[0x10] |= 0x06;
break;
case 2:
/* 1.2 Mb 5"5 drive */
s->cmos_data[0x10] |= 0x02;
break;
}
if (fd0 < 3)
nb++;
if (fd1 < 3)
nb++;
switch (nb) {
case 0:
break;
case 1:
s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
break;
case 2:
s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
break;
}
}
void speaker_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
speaker_data_on = (val >> 1) & 1;
pit_set_gate(&pit_channels[2], val & 1);
}
uint32_t speaker_ioport_read(CPUState *env, uint32_t addr)
{
int out;
out = pit_get_out(&pit_channels[2]);
dummy_refresh_clock ^= 1;
return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
(dummy_refresh_clock << 4);
}
/***********************************************************/
/* PC floppy disk controler emulation glue */
#define PC_FDC_DMA 0x2
#define PC_FDC_IRQ 0x6
#define PC_FDC_BASE 0x3F0
static void fdctrl_register (unsigned char **disknames, int ro,
char boot_device)
{
int i;
fdctrl_init(PC_FDC_IRQ, PC_FDC_DMA, 0, PC_FDC_BASE, boot_device);
for (i = 0; i < MAX_FD; i++) {
if (disknames[i] != NULL)
fdctrl_disk_change(i, disknames[i], ro);
}
}
/***********************************************************/
/* Bochs BIOS debug ports */
void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
{
switch(addr) {
/* Bochs BIOS messages */
case 0x400:
case 0x401:
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
exit(1);
case 0x402:
case 0x403:
#ifdef DEBUG_BIOS
fprintf(stderr, "%c", val);
#endif
break;
/* LGPL'ed VGA BIOS messages */
case 0x501:
case 0x502:
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
exit(1);
case 0x500:
case 0x503:
#ifdef DEBUG_BIOS
fprintf(stderr, "%c", val);
#endif
break;
}
}
void bochs_bios_init(void)
{
register_ioport_write(0x400, 1, bochs_bios_write, 2);
register_ioport_write(0x401, 1, bochs_bios_write, 2);
register_ioport_write(0x402, 1, bochs_bios_write, 1);
register_ioport_write(0x403, 1, bochs_bios_write, 1);
register_ioport_write(0x501, 1, bochs_bios_write, 2);
register_ioport_write(0x502, 1, bochs_bios_write, 2);
register_ioport_write(0x500, 1, bochs_bios_write, 1);
register_ioport_write(0x503, 1, bochs_bios_write, 1);
}
int load_kernel(const char *filename, uint8_t *addr,
uint8_t *real_addr)
{
int fd, size;
int setup_sects;
fd = open(filename, O_RDONLY);
if (fd < 0)
return -1;
/* load 16 bit code */
if (read(fd, real_addr, 512) != 512)
goto fail;
setup_sects = real_addr[0x1F1];
if (!setup_sects)
setup_sects = 4;
if (read(fd, real_addr + 512, setup_sects * 512) !=
setup_sects * 512)
goto fail;
/* load 32 bit code */
size = read(fd, addr, 16 * 1024 * 1024);
if (size < 0)
goto fail;
close(fd);
return size;
fail:
close(fd);
return -1;
}
/* PC hardware initialisation */
void pc_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
char buf[1024];
int ret, linux_boot, initrd_size;
linux_boot = (kernel_filename != NULL);
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, 0);
/* BIOS load */
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
ret = load_image(buf, phys_ram_base + 0x000f0000);
if (ret != 0x10000) {
fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
exit(1);
}
/* VGA BIOS load */
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
ret = load_image(buf, phys_ram_base + 0x000c0000);
/* setup basic memory access */
cpu_register_physical_memory(0xc0000, 0x10000, 0xc0000 | IO_MEM_ROM);
cpu_register_physical_memory(0xf0000, 0x10000, 0xf0000 | IO_MEM_ROM);
bochs_bios_init();
if (linux_boot) {
uint8_t bootsect[512];
if (bs_table[0] == NULL) {
fprintf(stderr, "A disk image must be given for 'hda' when booting a Linux kernel\n");
exit(1);
}
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, LINUX_BOOT_FILENAME);
ret = load_image(buf, bootsect);
if (ret != sizeof(bootsect)) {
fprintf(stderr, "qemu: could not load linux boot sector '%s'\n",
buf);
exit(1);
}
bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));
/* now we can load the kernel */
ret = load_kernel(kernel_filename,
phys_ram_base + KERNEL_LOAD_ADDR,
phys_ram_base + KERNEL_PARAMS_ADDR);
if (ret < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
/* load initrd */
initrd_size = 0;
if (initrd_filename) {
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
if (initrd_size < 0) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
}
if (initrd_size > 0) {
stl_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x218, INITRD_LOAD_ADDR);
stl_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x21c, initrd_size);
}
pstrcpy(phys_ram_base + KERNEL_CMDLINE_ADDR, 4096,
kernel_cmdline);
stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x20, 0xA33F);
stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x22,
KERNEL_CMDLINE_ADDR - KERNEL_PARAMS_ADDR);
/* loader type */
stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x210, 0x01);
}
/* init basic PC hardware */
register_ioport_write(0x80, 1, ioport80_write, 1);
vga_initialize(ds, phys_ram_base + ram_size, ram_size,
vga_ram_size);
rtc_init(0x70, 8);
cmos_init(ram_size, boot_device);
register_ioport_read(0x61, 1, speaker_ioport_read, 1);
register_ioport_write(0x61, 1, speaker_ioport_write, 1);
pic_init();
pit_init();
serial_init(0x3f8, 4);
ne2000_init(0x300, 9);
ide_init();
kbd_init();
AUD_init();
DMA_init();
SB16_init();
fdctrl_register((unsigned char **)fd_filename, snapshot, boot_device);
}
hw/pckbd.c 0 → 100644
浏览文件 @ 80cabfad
此差异已折叠。
hw/serial.c 0 → 100644
浏览文件 @ 80cabfad
/*
* QEMU 16450 UART emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>
#include "cpu.h"
#include "vl.h"
//#define DEBUG_SERIAL
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2 0x08 /* Out2 complement */
#define UART_MCR_OUT1 0x04 /* Out1 complement */
#define UART_MCR_RTS 0x02 /* RTS complement */
#define UART_MCR_DTR 0x01 /* DTR complement */
/*
* These are the definitions for the Modem Status Register
*/
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
#define UART_LSR_FE 0x08 /* Frame error indicator */
#define UART_LSR_PE 0x04 /* Parity error indicator */
#define UART_LSR_OE 0x02 /* Overrun error indicator */
#define UART_LSR_DR 0x01 /* Receiver data ready */
typedef struct SerialState {
uint8_t divider;
uint8_t rbr; /* receive register */
uint8_t ier;
uint8_t iir; /* read only */
uint8_t lcr;
uint8_t mcr;
uint8_t lsr; /* read only */
uint8_t msr;
uint8_t scr;
/* NOTE: this hidden state is necessary for tx irq generation as
it can be reset while reading iir */
int thr_ipending;
int irq;
} SerialState;
SerialState serial_ports[1];
void serial_update_irq(void)
{
SerialState *s = &serial_ports[0];
if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
s->iir = UART_IIR_RDI;
} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
s->iir = UART_IIR_THRI;
} else {
s->iir = UART_IIR_NO_INT;
}
if (s->iir != UART_IIR_NO_INT) {
pic_set_irq(s->irq, 1);
} else {
pic_set_irq(s->irq, 0);
}
}
void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
SerialState *s = &serial_ports[0];
unsigned char ch;
int ret;
addr &= 7;
#ifdef DEBUG_SERIAL
printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
switch(addr) {
default:
case 0:
if (s->lcr & UART_LCR_DLAB) {
s->divider = (s->divider & 0xff00) | val;
} else {
s->thr_ipending = 0;
s->lsr &= ~UART_LSR_THRE;
serial_update_irq();
ch = val;
do {
ret = write(1, &ch, 1);
} while (ret != 1);
s->thr_ipending = 1;
s->lsr |= UART_LSR_THRE;
s->lsr |= UART_LSR_TEMT;
serial_update_irq();
}
break;
case 1:
if (s->lcr & UART_LCR_DLAB) {
s->divider = (s->divider & 0x00ff) | (val << 8);
} else {
s->ier = val;
serial_update_irq();
}
break;
case 2:
break;
case 3:
s->lcr = val;
break;
case 4:
s->mcr = val;
break;
case 5:
break;
case 6:
s->msr = val;
break;
case 7:
s->scr = val;
break;
}
}
uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
{
SerialState *s = &serial_ports[0];
uint32_t ret;
addr &= 7;
switch(addr) {
default:
case 0:
if (s->lcr & UART_LCR_DLAB) {
ret = s->divider & 0xff;
} else {
ret = s->rbr;
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
serial_update_irq();
}
break;
case 1:
if (s->lcr & UART_LCR_DLAB) {
ret = (s->divider >> 8) & 0xff;
} else {
ret = s->ier;
}
break;
case 2:
ret = s->iir;
/* reset THR pending bit */
if ((ret & 0x7) == UART_IIR_THRI)
s->thr_ipending = 0;
serial_update_irq();
break;
case 3:
ret = s->lcr;
break;
case 4:
ret = s->mcr;
break;
case 5:
ret = s->lsr;
break;
case 6:
if (s->mcr & UART_MCR_LOOP) {
/* in loopback, the modem output pins are connected to the
inputs */
ret = (s->mcr & 0x0c) << 4;
ret |= (s->mcr & 0x02) << 3;
ret |= (s->mcr & 0x01) << 5;
} else {
ret = s->msr;
}
break;
case 7:
ret = s->scr;
break;
}
#ifdef DEBUG_SERIAL
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
return ret;
}
int serial_can_receive(void)
{
SerialState *s = &serial_ports[0];
return !(s->lsr & UART_LSR_DR);
}
void serial_receive_byte(int ch)
{
SerialState *s = &serial_ports[0];
s->rbr = ch;
s->lsr |= UART_LSR_DR;
serial_update_irq();
}
void serial_receive_break(void)
{
SerialState *s = &serial_ports[0];
s->rbr = 0;
s->lsr |= UART_LSR_BI | UART_LSR_DR;
serial_update_irq();
}
void serial_init(int base, int irq)
{
SerialState *s = &serial_ports[0];
s->irq = irq;
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
s->iir = UART_IIR_NO_INT;
register_ioport_write(base, 8, serial_ioport_write, 1);
register_ioport_read(base, 8, serial_ioport_read, 1);
}
vl.c
浏览文件 @ 80cabfad
此差异已折叠。
vl.h
浏览文件 @ 80cabfad
......@@ -29,21 +29,25 @@
/* vl.c */
extern int reset_requested;
extern int64_t ticks_per_sec;
extern int pit_min_timer_count;
typedef void (IOPortWriteFunc)(struct CPUState *env, uint32_t address, uint32_t data);
typedef uint32_t (IOPortReadFunc)(struct CPUState *env, uint32_t address);
int register_ioport_read(int start, int length, IOPortReadFunc *func, int size);
int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size);
void pic_set_irq(int irq, int level);
int64_t cpu_get_ticks(void);
uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
void kbd_put_keycode(int keycode);
void net_send_packet(int net_fd, const uint8_t *buf, int size);
#define MOUSE_EVENT_LBUTTON 0x01
#define MOUSE_EVENT_RBUTTON 0x02
#define MOUSE_EVENT_MBUTTON 0x04
void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
void hw_error(const char *fmt, ...);
int load_image(const char *filename, uint8_t *addr);
extern const char *bios_dir;
void pstrcpy(char *buf, int buf_size, const char *str);
char *pstrcat(char *buf, int buf_size, const char *s);
/* block.c */
typedef struct BlockDriverState BlockDriverState;
......@@ -139,4 +143,78 @@ void fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, uint32_t base,
char boot_device);
int fdctrl_disk_change (int idx, const unsigned char *filename, int ro);
/* ne2000.c */
#define MAX_ETH_FRAME_SIZE 1514
void ne2000_init(int base, int irq);
int ne2000_can_receive(void);
void ne2000_receive(uint8_t *buf, int size);
extern int net_fd;
/* pckbd.c */
void kbd_put_keycode(int keycode);
#define MOUSE_EVENT_LBUTTON 0x01
#define MOUSE_EVENT_RBUTTON 0x02
#define MOUSE_EVENT_MBUTTON 0x04
void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
void kbd_init(void);
/* mc146818rtc.c */
typedef struct RTCState {
uint8_t cmos_data[128];
uint8_t cmos_index;
int irq;
} RTCState;
extern RTCState rtc_state;
void rtc_init(int base, int irq);
void rtc_timer(void);
/* serial.c */
void serial_init(int base, int irq);
int serial_can_receive(void);
void serial_receive_byte(int ch);
void serial_receive_break(void);
/* i8259.c */
void pic_set_irq(int irq, int level);
void pic_init(void);
/* i8254.c */
#define PIT_FREQ 1193182
typedef struct PITChannelState {
int count; /* can be 65536 */
uint16_t latched_count;
uint8_t rw_state;
uint8_t mode;
uint8_t bcd; /* not supported */
uint8_t gate; /* timer start */
int64_t count_load_time;
int64_t count_last_edge_check_time;
} PITChannelState;
extern PITChannelState pit_channels[3];
void pit_init(void);
void pit_set_gate(PITChannelState *s, int val);
int pit_get_out(PITChannelState *s);
int pit_get_out_edges(PITChannelState *s);
/* pc.c */
void pc_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename);
#endif /* VL_H */
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