Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
qemu
提交
7cc09e6c
Q
qemu
项目概览
openeuler
/
qemu
通知
10
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
Q
qemu
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
7cc09e6c
编写于
10月 03, 2011
作者:
A
Avi Kivity
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
spitz: convert to memory API
Signed-off-by:
N
Avi Kivity
<
avi@redhat.com
>
上级
890c2b77
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
18 addition
and
30 deletion
+18
-30
hw/spitz.c
hw/spitz.c
+18
-30
未找到文件。
hw/spitz.c
浏览文件 @
7cc09e6c
...
@@ -49,6 +49,7 @@
...
@@ -49,6 +49,7 @@
typedef
struct
{
typedef
struct
{
SysBusDevice
busdev
;
SysBusDevice
busdev
;
MemoryRegion
iomem
;
DeviceState
*
nand
;
DeviceState
*
nand
;
uint8_t
ctl
;
uint8_t
ctl
;
uint8_t
manf_id
;
uint8_t
manf_id
;
...
@@ -56,7 +57,7 @@ typedef struct {
...
@@ -56,7 +57,7 @@ typedef struct {
ECCState
ecc
;
ECCState
ecc
;
}
SLNANDState
;
}
SLNANDState
;
static
uint
32_t
sl_readb
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
uint
64_t
sl_read
(
void
*
opaque
,
target_phys_addr_t
addr
,
unsigned
size
)
{
{
SLNANDState
*
s
=
(
SLNANDState
*
)
opaque
;
SLNANDState
*
s
=
(
SLNANDState
*
)
opaque
;
int
ryby
;
int
ryby
;
...
@@ -86,6 +87,10 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
...
@@ -86,6 +87,10 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
return
s
->
ctl
;
return
s
->
ctl
;
case
FLASH_FLASHIO
:
case
FLASH_FLASHIO
:
if
(
size
==
4
)
{
return
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
))
|
(
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
))
<<
16
);
}
return
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
));
return
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
));
default:
default:
...
@@ -94,19 +99,8 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
...
@@ -94,19 +99,8 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
return
0
;
return
0
;
}
}
static
uint32_t
sl_readl
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
void
sl_write
(
void
*
opaque
,
target_phys_addr_t
addr
,
{
uint64_t
value
,
unsigned
size
)
SLNANDState
*
s
=
(
SLNANDState
*
)
opaque
;
if
(
addr
==
FLASH_FLASHIO
)
return
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
))
|
(
ecc_digest
(
&
s
->
ecc
,
nand_getio
(
s
->
nand
))
<<
16
);
return
sl_readb
(
opaque
,
addr
);
}
static
void
sl_writeb
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
value
)
{
{
SLNANDState
*
s
=
(
SLNANDState
*
)
opaque
;
SLNANDState
*
s
=
(
SLNANDState
*
)
opaque
;
...
@@ -140,15 +134,10 @@ enum {
...
@@ -140,15 +134,10 @@ enum {
FLASH_1024M
,
FLASH_1024M
,
};
};
static
CPUReadMemoryFunc
*
const
sl_readfn
[]
=
{
static
const
MemoryRegionOps
sl_ops
=
{
sl_readb
,
.
read
=
sl_read
,
sl_readb
,
.
write
=
sl_write
,
sl_readl
,
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
static
CPUWriteMemoryFunc
*
const
sl_writefn
[]
=
{
sl_writeb
,
sl_writeb
,
sl_writeb
,
};
};
static
void
sl_flash_register
(
PXA2xxState
*
cpu
,
int
size
)
static
void
sl_flash_register
(
PXA2xxState
*
cpu
,
int
size
)
...
@@ -168,7 +157,6 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
...
@@ -168,7 +157,6 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
}
}
static
int
sl_nand_init
(
SysBusDevice
*
dev
)
{
static
int
sl_nand_init
(
SysBusDevice
*
dev
)
{
int
iomemtype
;
SLNANDState
*
s
;
SLNANDState
*
s
;
DriveInfo
*
nand
;
DriveInfo
*
nand
;
...
@@ -178,10 +166,8 @@ static int sl_nand_init(SysBusDevice *dev) {
...
@@ -178,10 +166,8 @@ static int sl_nand_init(SysBusDevice *dev) {
nand
=
drive_get
(
IF_MTD
,
0
,
0
);
nand
=
drive_get
(
IF_MTD
,
0
,
0
);
s
->
nand
=
nand_init
(
nand
?
nand
->
bdrv
:
NULL
,
s
->
manf_id
,
s
->
chip_id
);
s
->
nand
=
nand_init
(
nand
?
nand
->
bdrv
:
NULL
,
s
->
manf_id
,
s
->
chip_id
);
iomemtype
=
cpu_register_io_memory
(
sl_readfn
,
memory_region_init_io
(
&
s
->
iomem
,
&
sl_ops
,
s
,
"sl"
,
0x40
);
sl_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
sysbus_init_mmio_region
(
dev
,
&
s
->
iomem
);
sysbus_init_mmio
(
dev
,
0x40
,
iomemtype
);
return
0
;
return
0
;
}
}
...
@@ -898,6 +884,7 @@ static void spitz_common_init(ram_addr_t ram_size,
...
@@ -898,6 +884,7 @@ static void spitz_common_init(ram_addr_t ram_size,
PXA2xxState
*
cpu
;
PXA2xxState
*
cpu
;
DeviceState
*
scp0
,
*
scp1
=
NULL
;
DeviceState
*
scp0
,
*
scp1
=
NULL
;
MemoryRegion
*
address_space_mem
=
get_system_memory
();
MemoryRegion
*
address_space_mem
=
get_system_memory
();
MemoryRegion
*
rom
=
g_new
(
MemoryRegion
,
1
);
if
(
!
cpu_model
)
if
(
!
cpu_model
)
cpu_model
=
(
model
==
terrier
)
?
"pxa270-c5"
:
"pxa270-c0"
;
cpu_model
=
(
model
==
terrier
)
?
"pxa270-c5"
:
"pxa270-c0"
;
...
@@ -907,8 +894,9 @@ static void spitz_common_init(ram_addr_t ram_size,
...
@@ -907,8 +894,9 @@ static void spitz_common_init(ram_addr_t ram_size,
sl_flash_register
(
cpu
,
(
model
==
spitz
)
?
FLASH_128M
:
FLASH_1024M
);
sl_flash_register
(
cpu
,
(
model
==
spitz
)
?
FLASH_128M
:
FLASH_1024M
);
cpu_register_physical_memory
(
0
,
SPITZ_ROM
,
memory_region_init_ram
(
rom
,
NULL
,
"spitz.rom"
,
SPITZ_ROM
);
qemu_ram_alloc
(
NULL
,
"spitz.rom"
,
SPITZ_ROM
)
|
IO_MEM_ROM
);
memory_region_set_readonly
(
rom
,
true
);
memory_region_add_subregion
(
address_space_mem
,
0
,
rom
);
/* Setup peripherals */
/* Setup peripherals */
spitz_keyboard_register
(
cpu
);
spitz_keyboard_register
(
cpu
);
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录