提交 5f06b547 编写于 作者: T Tsuneo Saito 提交者: Blue Swirl

SPARC64: fp_disabled checks on stfa/stdfa/stqfa

stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
上级 e1ef36c4
......@@ -4732,6 +4732,9 @@ static void disas_sparc_insn(DisasContext * dc)
switch (xop) {
#ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */
if (gen_trap_ifnofpu(dc, cpu_cond)) {
goto jmp_insn;
}
gen_stf_asi(cpu_addr, insn, 4, rd);
break;
case 0x36: /* V9 stqfa */
......@@ -4739,6 +4742,9 @@ static void disas_sparc_insn(DisasContext * dc)
TCGv_i32 r_const;
CHECK_FPU_FEATURE(dc, FLOAT128);
if (gen_trap_ifnofpu(dc, cpu_cond)) {
goto jmp_insn;
}
r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
......@@ -4746,6 +4752,9 @@ static void disas_sparc_insn(DisasContext * dc)
}
break;
case 0x37: /* V9 stdfa */
if (gen_trap_ifnofpu(dc, cpu_cond)) {
goto jmp_insn;
}
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
......
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