target-tricore: Fix wrong precedences on psw_write
Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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