Fix new typos (found by codespell)

* accomodate -> accommodate
* aquiring -> acquiring
* beacuse -> because
* loosing -> losing
* prefering -> preferring
* threshhold -> threshold
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>

block/iscsi.c

@@ -101,7 +101,7 @@ typedef struct IscsiAIOCB {
 #define ISCSI_CMD_RETRIES ARRAY_SIZE(iscsi_retry_times)
 static const unsigned iscsi_retry_times[] = {8, 32, 128, 512, 2048};
 
-/* this threshhold is a trade-off knob to choose between
+/* this threshold is a trade-off knob to choose between
  * the potential additional overhead of an extra GET_LBA_STATUS request
  * vs. unnecessarily reading a lot of zero sectors over the wire.
  * If a read request is greater or equal than ISCSI_CHECKALLOC_THRES

hw/input/hid.c

@@ -164,7 +164,7 @@ static void hid_pointer_sync(DeviceState *dev)
 
     if (hs->n == QUEUE_LENGTH-1) {
         /*
-         * Queue full.  We are loosing information, but we at least
+         * Queue full.  We are losing information, but we at least
          * keep track of most recent button state.
          */
         return;

target-arm/helper.c

@@ -2350,7 +2350,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST,
-              /* We mask out the PMUVer field, beacuse we don't currently
+              /* We mask out the PMUVer field, because we don't currently
                * implement the PMU. Not advertising it prevents the guest
                * from trying to use it and getting UNDEFs on registers we
                * don't implement.

tcg/mips/tcg-target.c

@@ -781,7 +781,7 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
         break;
 
     default:
-        /* Minimize code size by prefering a compare not requiring INV.  */
+        /* Minimize code size by preferring a compare not requiring INV.  */
         if (mips_cmp_map[cond] & MIPS_CMP_INV) {
             cond = tcg_invert_cond(cond);
             b_cond = TCG_COND_EQ;
@@ -810,7 +810,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
         break;
 
     default:
-        /* Minimize code size by prefering a compare not requiring INV.  */
+        /* Minimize code size by preferring a compare not requiring INV.  */
         if (mips_cmp_map[cond] & MIPS_CMP_INV) {
             cond = tcg_invert_cond(cond);
             m_opc = OPC_MOVZ;

tests/qemu-iotests/common.qemu

@@ -103,7 +103,7 @@ function _send_qemu_cmd()
         count=${qemu_cmd_repeat}
         use_error="no"
     fi
-    # This array element extraction is done to accomodate pathnames with spaces
+    # This array element extraction is done to accommodate pathnames with spaces
     cmd=${@: 1:${#@}-1}
     shift $(($# - 1))
 

translate-all.c

@@ -594,7 +594,7 @@ static inline void *alloc_code_gen_buffer(void)
 
 #ifdef __mips__
     if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) {
-        /* Try again, with the original still mapped, to avoid re-aquiring
+        /* Try again, with the original still mapped, to avoid re-acquiring
            that 256mb crossing.  This time don't specify an address.  */
         size_t size2, size1 = tcg_ctx.code_gen_buffer_size;
         void *buf2 = mmap(NULL, size1, PROT_WRITE | PROT_READ | PROT_EXEC,