提交 593f17e5 编写于 作者: R Richard Henderson 提交者: Aurelien Jarno

target-alpha: Implement cvtlq inline.

It's a simple shift and mask sequence.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
上级 ac316ca4
......@@ -83,7 +83,6 @@ DEF_HELPER_FLAGS_1(cvtqf, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtgf, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtgq, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtqg, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtlq, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
DEF_HELPER_FLAGS_1(cvttq, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64)
......
......@@ -1152,13 +1152,6 @@ uint64_t helper_cvtqg (uint64_t a)
return float64_to_g(fr);
}
uint64_t helper_cvtlq (uint64_t a)
{
int32_t lo = a >> 29;
int32_t hi = a >> 32;
return (lo & 0x3FFFFFFF) | (hi & 0xc0000000);
}
/* PALcode support special instructions */
#if !defined (CONFIG_USER_ONLY)
void helper_hw_rei (void)
......
......@@ -598,6 +598,28 @@ static inline void gen_fp_exc_raise(int rc, int fn11)
gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
}
static void gen_fcvtlq(int rb, int rc)
{
if (unlikely(rc == 31)) {
return;
}
if (unlikely(rb == 31)) {
tcg_gen_movi_i64(cpu_fir[rc], 0);
} else {
TCGv tmp = tcg_temp_new();
/* The arithmetic right shift here, plus the sign-extended mask below
yields a sign-extended result without an explicit ext32s_i64. */
tcg_gen_sari_i64(tmp, cpu_fir[rb], 32);
tcg_gen_shri_i64(cpu_fir[rc], cpu_fir[rb], 29);
tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rc], 0x3fffffff);
tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp);
tcg_temp_free(tmp);
}
}
static void gen_fcvtql(int rb, int rc)
{
if (unlikely(rc == 31)) {
......@@ -647,7 +669,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \
tcg_temp_free(tmp); \
} \
}
FARITH2(cvtlq)
/* ??? VAX instruction qualifiers ignored. */
FARITH2(sqrtf)
......
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