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提交 4e290a0b 编写于 作者: J j_mayer
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Share input pins and internal interrupt controller between all PowerPC 40x. 

Fix critical input interrupt generation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162
上级 3391c818
隐藏空白更改
内联 并排
Showing with 41 addition and 39 deletion
hw/ppc.c
浏览文件 @ 4e290a0b
......@@ -284,8 +284,8 @@ void ppc970_irq_init (CPUState *env)
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
}
/* PowerPC 405 internal IRQ controller */
static void ppc405_set_irq (void *opaque, int pin, int level)
/* PowerPC 40x internal IRQ controller */
static void ppc40x_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
int cur_level;
......@@ -300,7 +300,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
case PPC405_INPUT_RESET_SYS:
case PPC40x_INPUT_RESET_SYS:
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
......@@ -311,7 +311,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
ppc40x_system_reset(env);
}
break;
case PPC405_INPUT_RESET_CHIP:
case PPC40x_INPUT_RESET_CHIP:
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
......@@ -321,8 +321,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
ppc40x_chip_reset(env);
}
break;
/* No break here */
case PPC405_INPUT_RESET_CORE:
case PPC40x_INPUT_RESET_CORE:
/* XXX: TODO: update DBSR[MRR] */
if (level) {
#if defined(PPC_DEBUG_IRQ)
......@@ -333,7 +332,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
ppc40x_core_reset(env);
}
break;
case PPC405_INPUT_CINT:
case PPC40x_INPUT_CINT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
......@@ -341,10 +340,9 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
__func__, level);
}
#endif
/* XXX: TOFIX */
ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
break;
case PPC405_INPUT_INT:
case PPC40x_INPUT_INT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
......@@ -354,7 +352,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPC405_INPUT_HALT:
case PPC40x_INPUT_HALT:
/* Level sensitive - active low */
if (level) {
#if defined(PPC_DEBUG_IRQ)
......@@ -372,7 +370,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
env->halted = 0;
}
break;
case PPC405_INPUT_DEBUG:
case PPC40x_INPUT_DEBUG:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
......@@ -398,9 +396,10 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
}
}
void ppc405_irq_init (CPUState *env)
void ppc40x_irq_init (CPUState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
env, PPC40x_INPUT_NB);
}
/*****************************************************************************/
......
target-ppc/cpu.h
浏览文件 @ 4e290a0b
......@@ -1117,23 +1117,15 @@ enum {
};
enum {
/* PowerPC 401/403 input pins */
PPC401_INPUT_RESET = 0,
PPC401_INPUT_CINT = 1,
PPC401_INPUT_INT = 2,
PPC401_INPUT_BERR = 3,
PPC401_INPUT_HALT = 4,
};
enum {
/* PowerPC 405 input pins */
PPC405_INPUT_RESET_CORE = 0,
PPC405_INPUT_RESET_CHIP = 1,
PPC405_INPUT_RESET_SYS = 2,
PPC405_INPUT_CINT = 3,
PPC405_INPUT_INT = 4,
PPC405_INPUT_HALT = 5,
PPC405_INPUT_DEBUG = 6,
/* PowerPC 40x input pins */
PPC40x_INPUT_RESET_CORE = 0,
PPC40x_INPUT_RESET_CHIP = 1,
PPC40x_INPUT_RESET_SYS = 2,
PPC40x_INPUT_CINT = 3,
PPC40x_INPUT_INT = 4,
PPC40x_INPUT_HALT = 5,
PPC40x_INPUT_DEBUG = 6,
PPC40x_INPUT_NB,
};
enum {
......
target-ppc/translate_init.c
浏览文件 @ 4e290a0b
......@@ -54,8 +54,7 @@ static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
#endif
PPC_IRQ_INIT_FN(401);
PPC_IRQ_INIT_FN(405);
PPC_IRQ_INIT_FN(40x);
PPC_IRQ_INIT_FN(6xx);
PPC_IRQ_INIT_FN(970);
......@@ -2482,7 +2481,8 @@ static void init_proc_401 (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
init_excp_4xx_real(env);
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
/* PowerPC 401x2 */
......@@ -2518,7 +2518,8 @@ static void init_proc_401x2 (CPUPPCState *env)
env->nb_ways = 1;
env->id_tlbs = 0;
init_excp_4xx_softmmu(env);
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
/* PowerPC 401x3 */
......@@ -2536,7 +2537,14 @@ static void init_proc_401x2 (CPUPPCState *env)
static void init_proc_401x3 (CPUPPCState *env)
{
gen_spr_40x(env);
gen_spr_401_403(env);
gen_spr_401(env);
gen_spr_401x2(env);
gen_spr_compress(env);
init_excp_4xx_softmmu(env);
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
#endif /* TODO */
......@@ -2573,7 +2581,8 @@ static void init_proc_IOP480 (CPUPPCState *env)
env->nb_ways = 1;
env->id_tlbs = 0;
init_excp_4xx_softmmu(env);
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
/* PowerPC 403 */
......@@ -2594,7 +2603,8 @@ static void init_proc_403 (CPUPPCState *env)
gen_spr_403(env);
gen_spr_403_real(env);
init_excp_4xx_real(env);
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
/* PowerPC 403 GCX */
......@@ -2630,7 +2640,8 @@ static void init_proc_403GCX (CPUPPCState *env)
env->nb_ways = 1;
env->id_tlbs = 0;
init_excp_4xx_softmmu(env);
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
}
/* PowerPC 405 */
......@@ -2667,7 +2678,7 @@ static void init_proc_405 (CPUPPCState *env)
env->id_tlbs = 0;
init_excp_4xx_softmmu(env);
/* Allocate hardware IRQ controller */
ppc405_irq_init(env);
ppc40x_irq_init(env);
}
/* PowerPC 440 EP */
......
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