target-ppc: Store Quadword Conditional Drops Size Bit
The size and register information are encoded into the reserve_info field of CPU state in the store conditional translation code. Specifically, the size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store). The user-mode store conditional code erroneously extracts the size by ANDing with a 4 bit mask; this breaks if size >= 16. Eliminate the mask to make the extraction of size mirror its encoding. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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