提交 4abf12f4 编写于 作者: J Julian Pidancet 提交者: Stefan Hajnoczi

rtl8139: Fix invalid IO access alignment

This patch makes iPXE work with the rtl8139 emulation. The rtl8139
driver in iPXE issues a 16bit access on the ChipCmd register
(offset 0x37) to check the status of the rx buffer. The offset of the
ioport access was getting fixed up to 0x36 in qemu, causing the value
read in iPXE to be invalid.

This fixes an issue with iPXE reporting timeouts during TFTP transfers.

Reposting this here because it is trivial enough and the original post
on qemu-devel didn't attract much attention.

Also, the inw() which was causing the issue has been replaced with an
inb() in upstream iPXE:
https://git.ipxe.org/ipxe.git/commit/91dd64ad25baa27954a7518e73df4fca8a2d0c93Signed-off-by: NJulian Pidancet <julian.pidancet@gmail.com>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
上级 e30e5eb6
...@@ -1971,7 +1971,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s) ...@@ -1971,7 +1971,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
cplus_tx_ring_desc += 16 * descriptor; cplus_tx_ring_desc += 16 * descriptor;
DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
"%08x0x%08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
s->TxAddr[0], cplus_tx_ring_desc); s->TxAddr[0], cplus_tx_ring_desc);
uint32_t val, txdw0,txdw1,txbufLO,txbufHI; uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
...@@ -2713,8 +2713,6 @@ static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) ...@@ -2713,8 +2713,6 @@ static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
{ {
RTL8139State *s = opaque; RTL8139State *s = opaque;
addr &= 0xff;
switch (addr) switch (addr)
{ {
case MAC0 ... MAC0+5: case MAC0 ... MAC0+5:
...@@ -2800,8 +2798,6 @@ static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) ...@@ -2800,8 +2798,6 @@ static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
{ {
RTL8139State *s = opaque; RTL8139State *s = opaque;
addr &= 0xfe;
switch (addr) switch (addr)
{ {
case IntrMask: case IntrMask:
...@@ -2900,8 +2896,6 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) ...@@ -2900,8 +2896,6 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
{ {
RTL8139State *s = opaque; RTL8139State *s = opaque;
addr &= 0xfc;
switch (addr) switch (addr)
{ {
case RxMissed: case RxMissed:
...@@ -2969,8 +2963,6 @@ static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) ...@@ -2969,8 +2963,6 @@ static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
RTL8139State *s = opaque; RTL8139State *s = opaque;
int ret; int ret;
addr &= 0xff;
switch (addr) switch (addr)
{ {
case MAC0 ... MAC0+5: case MAC0 ... MAC0+5:
...@@ -3043,8 +3035,6 @@ static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) ...@@ -3043,8 +3035,6 @@ static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
RTL8139State *s = opaque; RTL8139State *s = opaque;
uint32_t ret; uint32_t ret;
addr &= 0xfe; /* mask lower bit */
switch (addr) switch (addr)
{ {
case IntrMask: case IntrMask:
...@@ -3120,8 +3110,6 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) ...@@ -3120,8 +3110,6 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
RTL8139State *s = opaque; RTL8139State *s = opaque;
uint32_t ret; uint32_t ret;
addr &= 0xfc; /* also mask low 2 bits */
switch (addr) switch (addr)
{ {
case RxMissed: case RxMissed:
......
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